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doc. no. e0643e30 (ver. 3.0) date published august 2005 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2005 overview the edx5116abse is a 512m bits xdr ? dram organized as 32m words 16 bits. it is a general-purpose high-perfor- mance memory device suitable for use in a broad range of applications. the use of differential rambus signaling level (drsl) tech- nology permits 4000/3200/2400 mb/s transfer rates while using conventional system and board design technologies. xdr dram devices are capable of sustained data transfers of 8000/6400/4800 mb/s. xdr dram device architecture allows the highest sustained bandwidth for multiple, interl eaved randomly addressed mem- ory transactions. the highly-effi cient protocol yields over 95% utilization while allowing fine access granularity. the device?s eight banks support up to four interleaved transactions. it is packaged in 104-ball fbga ( bga ? ) compatible with rambus xdr dram pin configuration. features ? highest pin bandwidth available 4000/3200/2400 mb/s octal data rate (odr) signaling ? bi-directional differential rsl (drsl) - flexible read/write bandwidth allocation - minimum pin count ? on-chip termination -adaptive impedance matching -reduced system cost and routing complexity ? highest sustained bandwidth per dram device ? 8000/6400/4800 mb/s sustained data rate ? eight banks: bank-interle aved transactions at full bandwidth ? dynamic request scheduling ? early-read-after-write support for maximum efficiency ? zero overhead refresh ? dynamic width control ?edx5116abse supports 16, 8 and 4 mode ?low latency ? 2.0/2.5/3.33 ns request packets ? point-to-point data inte rconnect for fastest possible flight time ? support for low-latenc y, fast-cycle cores ?low power ? 1.8v vdd ? programmable small-swing i/o signaling (drsl) ? low power pll/dll design ? powerdown self-refresh support ? per pin i/o powerdown for narrow-width operation pin configuration 7 6 5 4 3 2 1 dq7 dqn7 dqn5 dq5 gnd vterm vdd gnd dq3 dqn3 dqn1 dq1 gnd rq11 rq10 gnd vdd rq9 rq8 vdd gnd rq7 rq6 vdd cfm cfmn rq4 vref gnd rq5 rq2 gnd vdd rq3 rq0 vdd gnd rq1 rst gnd sd1 sck cmd sd0 dg2 dqn2 dqn0 dq0 gnd vterm vdd gnd dq6 dqn6 dqn4 dq4 g f e d c b a p n m l k j h column row a8 a16 e f h j k l 5 6 7 8 9 10 11 1 2 3 4 dqn9 dq9 dqn5 dq5 gnd vterm vdd vdd vdd gnd vterm gnd rq10 rq11 gnd gnd vdd rq4 rq3 vdd vdd sdi gnd rq0 gnd vterm dqn8 dq8 dqn4 vdd gnd vterm gdcba vdd dq4 top view of package cfm cfmn gnd vdd vdd gnd gnd rsrv rsrv vdd gnd dqn2 dq2 dqn14 vdd gnd gnd dq14 dqn3 dq3 dqn15 vdd gnd gnd dq15 12 13 14 15 16 gnd dqn13 dq13 dqn1 dq1 vdd cmd sck gnd rq9 rq8 vdd rq1 rq2 vdd gnd vdd gnd rst sdo gnd dqn12 dq12 dqn0 dq0 rq7 rq6 vdd vref rq5 vdd dqn6 dq6 dqn10 dq10 vdd dqn7 dq7 dqn11 dq11 gnd gnd gnd vdd vdd 512m bits xdr ? dram edx5116abse (32m words 16 bits) preliminary data sheet
preliminary data sheet e0643e30 (ver. 3.0) 2 edx5116abse e lpida memory d ensity 25: 256m (x 16bit) o rganization 16: x16bit p ower supply, interface a: 1.8v, drsl die rev. package se: fbga ( bga with back cover) p roduct family x: xdr dram t ype d: monolithic device e d x 51 16 a b se - 4c - e environment code e: lead free speed 4c: 4.0g (trac = 28, c bin ) 3c: 3.2g (trac = 35, c bin ) 3b: 3.2g (trac = 35, b bin ) 3a: 3.2g (trac = 27, a bin ) 2a: 2.4g (trac = 36, a bin ) ordering information part number part number organization bandwidth (1/tbit) latency (trac) bin package edx5116abse-4c-e edx5116abse-3c-e EDX5116ABSE-3B-E edx5116abse-3a-e edx5116abse-2a-e 4m 16 8 banks 4.0g 3.2g 3.2g 3.2g 2.4g 28 35 35 27 36 c c b a a 104-ball fbga ( bga)
preliminary data sheet e0643e30 (ver. 3.0) 3 edx5116abse general description the timing diagrams in figure 1 illustrate xdr dram device write and read transactions. ther e are three sets of pins used for normal memory access transactions: cfm/cfmn clock pins, rq11..0 request pins, and dq15..0/dqn15..0 data pins. the ?n? appended to a signal name denotes the complemen- tary signal of a differential pair. a transaction is a collection of packets needed to complete a memory access. a packet is a set of bit windows on the signals of a bus. there are two buses that carry packets: the rq bus and dq bus. each packet on the rq bus uses a set of 2 bit- windows on each signal, while the dq bus uses a set of 16 bit- windows on each signal. in the write transaction shown in figure 1, a request packet (on the rq bus) at clock edge t 0 contains an activate (act) com- mand. this causes row ra of bank ba in the memory compo- nent to be loaded into the sense amp array for the bank. a second request packet at clock edge t 1 contains a write (wr) command. this causes the data packet d(a1) at edge t 4 to be written to column ca1 of the sense amp array for bank ba. a third request packet at clock edge t 3 contains another write (wr) command. this causes the data packet d(a2) at edge t 6 to be also written to column ca2. a final request packet at clock edge t 14 contains a precharge (pre) command. the spacings between the request packets are constrained by the following timing parameters in the diagram: t rcd -w , t cc , and t wrp . in addition, the spacing between the request packets and data packets are constrained by the t cwd parameter. the spacing of the cfm/cfmn clock edges is constrained by t cycle . figure 1 xdr dram device write and read transactions the read transaction shows a request packet at clock edge t 0 containing an act command. this causes row ra of bank ba of the memory component to load into the sense amp array for the bank. a second request packet at clock edge t 5 contains a read (rd) command. this causes the data packet q(a1) at edge t 11 to be read from column ca 1 of the sense amp array for bank ba. a third request packet at clock edge t 7 contains another rd command. this caus es the data packet q(a2) at edge t 13 to also be read from column ca2. a final request packet at clock edge t 10 contains a pre command. the spac- ings between the request packet s are constrained by the follow- ing timing parameters in the diagram: t rcd -r , t cc , and t rdp . in addition, the spacing between the request and data packets are constrained by the t cac parameter. t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a : wr a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cc t cwd t cycle t wrp t rcd-w a1 wr a2 wr a3 pre a0 act d(a2) d(a1) write transaction dq15..0 dqn15..0 cfm cfmn rq11..0 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: rd a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cc t cac t cycle t rdp t rcd-r a1 rd a2 rd a3 pre a0 act q(a2) q(a1) read transaction dq15..0 dqn15..0 cfm cfmn rq11..0
preliminary data sheet e0643e30 (ver. 3.0) 4 edx5116abse table of contents overview ....................................................................... 1 features ........................................................................ 1 pin configuration ......................................................... 1 ordering information ................................................... 2 part number .................................................................2 general description ......................................................3 table of contents .........................................................4 pin description .............................................................7 block diagram ..............................................................8 request packets ......................................................... 10 request packet formats ................................................. 10 request field encoding .................................................. 12 request packet interactions ........................................... 14 request interaction cases .............................................. 15 dynamic request scheduling ........................................ 20 memory operations .................................................... 22 write transactions .......................................................... 22 read transactions ........................................................... 24 interleaved transactions ................................................. 26 read/write interaction .................................................. 28 propagation delay ........................................................... 28 register operations .................................................... 32 serial transactions ........................................................... 32 serial write transaction ................................................. 32 serial read transaction .................................................. 32 register summary ............................................................ 34 maintenance operations ............................................ 40 refresh transactions ....................................................... 40 interleaved refresh transactions .................................. 40 calibration transactions ................................................. 42 power state management ............................................... 44 initialization ...................................................................... 46 xdr dram initialization overview .......................... 47 xdr dram pattern load with wdsl reg ............. 48 special feature description ....................................... 50 dynamic width control ................................................. 50 write masking .................................................................. 52 multiple bank sets and the eraw feature ................ 54 simultaneous activation ................................................. 56 simultaneous precharge ................................................. 57 operating conditions ................................................ 58 electrical conditions ....................................................... 58 timing conditions .......................................................... 59 operating characteristics .......................................... 60 electrical characteristics ................................................ 60 supply current profile .................................................... 61 timing characteristics .................................................... 62 timing parameters .......................................................... 62 receive/transmit timing .... ................ ............. ........ 64 clocking ............................................................................ 64 rsl rq receive timing ................................................ 65 drsl dq receive timing ............................................ 66 drsl dq transmit timing ......................................... 68 serial interface receive timing ..................................... 70 serial interface transmit timing .................................. 71 package description .................................................. 72 package parasitic summary ............................................ 72 package drawing ............................................................ 74 package pin numbering ................................................. 75 recommended soldering conditions ....................... 76
preliminary data sheet e0643e30 (ver. 3.0) 5 edx5116abse list of tables pin description .............................................................7 request field description .......................................... 10 op field encoding summary .................................... 12 rop field encoding summary .................................. 12 pop field encoding summary .................................. 13 xop field encoding summary .................................. 13 packet interaction summary ...................................... 14 scmd field encoding summary ............................... 32 initialization timing parame ters ............................... 47 xdr dram wdsl-to-core/dq/sc map (first genera- tion x16/x8/x4 xdr dram , bl=16) ...................... 48 core data word-to-wdsl fo rmat ............................ 49 electrical conditions .................................................. 58 timing conditions ..................................................... 59 electrical characteristics ........................................... 60 supply current profile ........ ................ ................ .........61 timing characteristics ............................................... 62 timing parameters .................................................... 62 package parasitic summary ....................................... 72
preliminary data sheet e0643e30 (ver. 3.0) 6 edx5116abse list of figures xdr dram device write and read transactions .....3 512mb (8x4mx16) xdr dram block diagram ..........9 request packet formats ..............................................11 act-, rd-, wr-, pre-to-act packet interactions . 16 act-, rd-, wr-, pre-to-rd packet interactions ... 17 act-, rd-, wr-, pre-to-wr packet interactions ... 18 act-, rd, wr-, pre-to-pre packet interactions .. 19 request scheduling examples ................................... 21 write transactions ..................................................... 23 read transactions ...................................................... 25 interleaved transactions ............................................ 27 write/read interaction .............................................. 29 propagation delay ...................................................... 31 serial write transaction ............................................. 33 serial read transaction ? selected dram .............. 33 serial read transaction ? non-selected dram ..... 33 serial identification (sid) register ............................ 34 configuration (cfg) register .................................... 35 power management (pm) register ............................ 35 write data serial load (wdsl) control register ..... 35 rq scan high (rqh) register ................................. 36 rq scan low (rql) register .................................... 36 refresh bank (refb) control register ..................... 36 refresh high (refh) row register ......................... 37 refresh middle (refm) row register ..................... 37 refresh low (refl) row register ........................... 37 io configuration (iocfg) register .......................... 37 current calibration 0 (cc0) register ........................ 38 current calibration 1 (cc1) register ......................... 38 read only memory 0 (rom0) register .................... 38 read only memory 1 (rom1) register .................... 38 test register ............................................................ 39 delay (dly) control register ................................... 39 refresh transactions ..................................................41 calibration transactions ............................................ 43 power state management .......................................... 45 serial interface system topology .............................. 46 initialization timing for xdr dram[k] device .... 46 multiplexers for dynamic width control .................. 50 d-to-s and s-to-q mapping for dynamic width control 51 byte mask logic ........................................................ 52 write-masked (wrm) transaction example ........... 53 write/read interaction ? no eraw feature ......... 54 write/read interaction ? eraw feature ............... 54 xdr dram block diagram with bank sets .......... 55 simultaneous activation ? trr-d cases ................. 56 simultaneous precharge ? tpp-d cases .................. 57 clocking waveforms .................................................. 64 rsl rq receive waveforms ..................................... 65 drsl dq receive waveforms .................................. 67 drsl dq transmit waveforms ................................ 69 serial interface receive waveforms ........................... 70 serial interface transmit waveforms .........................71 equivalent circuits for package parasitic ................. 73 csp x16 package - pin numbering (top view) .......... 75
preliminary data sheet e0643e30 (ver. 3.0) 7 edx5116abse pin description table 1 summarizes the pin fu nctionality of the xdr dram device. the first group of pins provide the necessary supply voltages. these include vdd and gnd for the core and inter- face logic, vref for receiving input signals, and vterm for driving output signals. the next group of pins are used for high bandwidth memory accesses. these include dq15..0 and dqn15..0 for carrying read and write data signals, rq 11..0 for carrying request sig- nals, and cfm and cfmn for carrying timing information used by the dq, dqn, and rq signals. the final set of pins comprise th e serial interface that is used for control register accesses. these include rst for initializing the state of the device, cmd fo r carrying command signals, sdi, and sdo for carrying register read data, and sck for car- rying the timing information used by the rst, sdi, sdo, and cmd signals. table 1 pin description signal i/o type no. of pins description vdd - - 22 supply voltage for the core and interface logic of the device. gnd - - 24 ground reference for the core and interface logic of the device. vref - - 1 logic threshold reference voltage for rsl signals. vterm - - 4 termination voltage for drsl signals. dq15..0 i/o drsl a 16 positive data signals that carry write or read data to and from the device. dqn15..0 i/o drsl a 16 negative data signals that carry write or read data to and from the device. rq11..0 i rsl a 12 request signals that carry control an d address information to the device. cfm i diffclk a 1 clock from master ? positive interface clock used for receiving rsl signals, and receiving and transmitting drsl signals from the channel. cfmn i diffclk a 1 clock from master ? negative interface clock used for receiving rsl signals, and receiving and transmitting drsl signals from the channel. rst i rsl a 1 reset input ? this pin is used to initialize the device. cmd i rsl a 1 command input ? this pin carries command , address, and control register write data into the device. sck i rsl a 1 serial clock input ? clock source used for reading from and writing to the con- trol registers. sdi i rsl a 1 serial data input ? this pin carries contro l register read data through the device. this pin is also used to initialize the device. sdo o cmos a 1 serial data output ? this pi n carries control register re ad data from the device. this pin is also used to initialize the device. rsrv - - 2 reserved pins ? follow rambus xdr syst em design guidelines for connecting rsrv pins total pin count per package 104 a. all dq and cfm signals are hi gh-true; low voltage is logic 0 and high voltage is logic 1. all dqn, cfmn, rq, rsl, and cmos si gnals are low-true; high voltage is logic 0 and low voltage is logic 1.
preliminary data sheet e0643e30 (ver. 3.0) 8 edx5116abse block diagram a block diagram of the xdr dram device is shown in figure 2. it shows all interface pins and major internal blocks. the cfm and cfmn clock signals are received and used by the clock generation logic to produce three virtual clock sig- nals: 1/t cycle , 2/t cycle , and 16/t cc . the frequency of these signals are 1x, 2x, and 8x that of the cfm and cfmn signals. these virtual signals show the ef fective data rate of the logic blocks to which they connect; th ey are not necessarily present in the actual memory component. the rq11..0 pins receive the re quest packet. two 12-bit words are received in one t cycle interval. this is indicated by the 2/ t cycle clocking signal connected to the 1:2 demux block that assembles the 24-bit request packet. these 24 bits are loaded into a register (clocked by the 1/t cycle clocking signal) and decoded by the decode block. the vref pin supplies a refer- ence voltage used by the rq receivers. three sets of control signals are produced by the decode block. these include the bank (ba) and row (r) addresses for an activate (act) command, the bank (br) and row (refr) addresses for a refresh activate (refa) command, the bank (bp) address for a precharge (p re) command, the bank (br) address for a refresh precharge (refp) command, and the bank (bc) and column (c and sc ) addresses for a read (rd) or write (wr or wrm) command. in addition, a mask (m) is used for a masked write (wrm) command. these commands can all be optiona lly delayed in increments of t cycle under control of delay fields in the request. the control signals of the commands are loaded into registers and pre- sented to the memory core. these registers are clocked at max- imum rates determined by core timing parameters, in this case 1/t rr , 1/t pp , and 1/t cc (1/4, 1/4, and 1/2 the frequency of cfm in the -3200 component). th ese registers may be loaded at any t cycle rising edge. once load ed, they should not be changed until a t rr , t pp , or t cc time later because timing paths of the memory core need time to settle. a bank address is decoded for an act command. the indi- cated row of the selected bank is sensed and placed into the associated sense amp array for the bank. sensing a row is also referred to as ?opening a page? for the bank. another bank address is deco ded for a pre command. the indicated bank and associated sense amp array are precharged to a state in which a subsequent act command can be applied. precharging a bank is al so called ?closing the page? for the bank. after a bank is given an act command and before it is given a pre command, it may receive read (rd) and write (wr) col- umn commands. these commands permit the data in the bank?s associated sense amp array to be accessed. for a wr command, the bank address is decoded. the indi- cated column of the associated sense amp array of the selected bank is written with the data received from the dq15..0 pins. the bank address is decoded for a rd command. the indi- cated column of the selected bank ?s associated sense amp array is read. the data is tran smitted onto the dq15..0 pins. the dq15..0 pins receive the write data packet (d) for a write transaction. 16 sixteen-bit wo rds are received in one t cc inter- val. this is indicated by the 16/t cc clocking signal connected to the 1:16 demux block that assembles the 16x16-bit write data packet. the write data is then driven to the selected sense amp array bank. 16 sixteen-bit words are accessed in the selected sense amp array bank for a read transacti on. the dq15..0 pins transmit this read data pa cket (q) in one t cc interval. this is indicated by the 16/t cc clocking signal connected to the 16:1 mux block. the vterm pin supplies a termination voltage for the dq pins. the rst, sck, and cmd pins co nnect to the control register block. these pins supply the da ta, address, and control needed to write the control registers. the read data for the these regis- ters is accessed through the sdo/sdi pins. these pins are also used to initialize the device. the control registers are used to transition between power modes, and are also used for calibrating the high speed trans- mit and receive circuits of the device. the control registers also supply bank (refb) and row (r efr) addresses for refresh operations.
preliminary data sheet e0643e30 (ver. 3.0) 9 edx5116abse figure 2 512mb (8x4mx16) xdr dram block diagram 1 1:2 demux decode 12 rq11..0 1:16 demux 16:1 mux 16/t cc 2/t cycle reg 12 12 cfm cfmn 1/t cycle 1/t cycle 12 12 4 rst,sck,cmd,sdi control registers 1 sdo 2/t cycle 16/ t cc bank 0 act delay reg 1/t rr act logic ... . . . {0..1}*t cycle decode bank 0 1 act act row 1 1/t pp ... decode 1 pre pre pre delay pre logic {0..3}*t cycle row . . . sense amp 0 ... 1 reg 1/t cc ... decode 1 r/w r/w col col rd,wr col logic .. . . .. reg 7 ba,br,refb r,refr bp,br,refb bc c sc m . . . bank array sense amp array 8 ... ... ... ... dynamic width demux (wr) reg termination vterm 2 1 vref refb,refr width {0..1}*t cycle delay dq15..0 dqn15..0 16 16 16 16 16/t cc 16x16*2 6 16x16 16x16 16x16 16x16 4 3 3 3 3 3 6+4 12 (2 3 - 1) bank (2 3 - 1) sense amp 2 3 2 3 3 6 16x16*2 6 12 2 3 16x16*2 6 *2 12 16 d[15:0][15:0] s[15:0][15:0] 16 16x16 16x16 16x16*2 6 width q[15:0][15:0] dynamic width mux (rd) byte mask (wr) power mode logic calibration logic refresh logic initialization logic
preliminary data sheet e0643e30 (ver. 3.0) 10 edx5116abse request packets a request packet carries address and control information to the memory device. this secti on contains tables and diagrams for packet formats, field enco dings and packet interactions. request packet formats there are five types of request packets: 1. rowa ? specifies an act command 2. col ? specifies rd and wr commands 3. colm ? specifies a wrm command 4. rowp ? specifies pre and ref commands 5. colx ? specifies the remaining commands table 2 describes fields within different request packet types. various request packet type fo rmats are illustrated in figure 3. each packet type consists of 24 bits sampled on the rq11..0 pins on two successive edges of the cfm/cfmn clock. the request packet formats are distin guished by the op3..0 field. this field also specifies the ope ration code of the desired com- mand. in the rowa packet, a bank address (ba), row address (r), and command delay (dela) are specified for the activate (act) command. in the col packet, a bank addr ess (bc), column address (c), sub-column address (sc), command delay (delc), and sub- opcode (wrx) are specified for the read (rd) and write (wr) commands. in the colm packet, a bank address (bc), column address (c), sub-column address (sc), and mask field (m) are specified for the masked write (wrm) command. in the rowp packet, two independent commands may be specified. a bank address (b p) and sub-opcode (pop) are specified for the precharge (pre) commands. an address field (ra) and sub-opcode (rop) ar e specified for the refresh (ref) commands. in the colx packet, a sub-operation code field (xop) is spec- ified for the remaining commands. table 2 request field description field packet types description op3..0 rowa/rowp/col/colm/colx 4-bit operation code that specifies packet format. (encoded commands are in table 3 on page 12). dela rowa delay the associated row activate command by 0 or 1 t cycle . ba2..0 rowa 3-bit bank address for row activate command. r11..0 rowa 12-bit row address for row activate command. wrx col specifies rd (=0) or wr (=1) command. delc col delay the column read or write command by 0 or 1 t cycle . bc2..0 col/colm 3-bit bank address fo r column read or write command. c9..4 col/colm 6-bit column address for column read or write command. sc3..0 col/colm 4-bit sub-column address for dynami c width (see ?dynamic width control? on page 50). m7..0 colm 8-bit mask for masked-write command wrm. pop2..0 rowp 3-bit operation code that specifies ro w precharge command with a delay of 0 to 3 t cycle . (encoded commands are in table 5 on page 13). bp2..0 rowp 3-bit bank addres s for row precharge command. rop2..0 rowp 3-bit operation code that specifies refresh commands. (encoded commands are in table 4 on page 12). ra7..0 rowp 8-bit refresh address fiel d (specifies br bank address, delay value, and refr load value xop3..0 colx 4-bit extended operati on code that specifies calibration and powerdown commands. (encoded commands are in table 6 on page 13).
preliminary data sheet e0643e30 (ver. 3.0) 11 edx5116abse figure 3 request packet formats t 0 t 1 t 2 t 3 cfm rq11..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn t cycle a3 pre a1 rd a2 wrm a0 act rq11 rowa packet rq10 rq9 rq8 rq7 rq6 rq5 rq4 rq3 rq2 rq1 rq0 cfm cfmn op del op r r r r r r r r r rsrv rsrv col packet op del op rsrv op rsrv wr c c bc bc colm packet op m m m m m m c c rowp packet op pop op rop op rop pop ra pop ra ra ra ra ra bp ra bp ra colx packet op rsrv op rsrv op rsrv op rsrv rsrv rsrv rsrv rsrv rsrv rsrv rsrv rsrv xop rsrv xop rsrv xop rsrv xop rsrv - pdn t cycle t cycle t cycle t cycle t cycle 2 2 c a 3 2 3 2 0 x7 0 1 2 3 4 5 6 7 8 3 3 1 0 7 6 4 7 6 3 2 0 1 0 7 6 6 3 2 1 0 0 dq15..0 dqn15..0 cfm cfmn rq11..0 3 2 1 0 ba 1 ba 0 rsrv op 1 c 5 c 4 c 5 m 5 m 2 rop 1 op 1 bc 1 bc 0 c 4 0 1 0 1 2 3 4 5 1 0 9 r 10 r 11 r rsrv rsrv 2 ba rsrv rsrv 8 c rsrv 2 bc 9 c rsrv 1 sc 0 sc 3 sc 2 sc 8 c rsrv 2 bc 9 c rsrv 1 sc 0 sc 3 sc 2 sc rsrv 2 bp rsrv rsrv
preliminary data sheet e0643e30 (ver. 3.0) 12 edx5116abse request field encoding operation-code fields are encoded within different packet types to specify commands. table 3 through table 6 provides packet type and encoding summaries. table 3 shows the op field encoding for the five packet types. the colm and rowa packets each specify a single com- mand: act and wrm. the col, colx, and rowp packets each use additional fields to specify multiple commands: wrx, xop, and pop/rop, respectively. the colm packet specifies the masked write command wrm. this is like the wr unmasked write command, except that a mask field m7..0 indi- cates whether each byte of the wr ite data packet is written or not written. the rowa packet specifies the row activate com- mand act. the col packet uses the wrx field to specify the column read and column wr ite (unmasked) commands. encoding of the rop field in the rowp packet is shown in table 4. the first encoding sp ecifies a nopr (no operation) command. the refp command uses the ra field to select a bank to be precharged. the refa and refi commands use the ra field and refh/m/l registers to select a bank and row to be activated for refr esh. the refi command also increments the refh/m/l register. the refp, refa, and refi commands may also be delayed by up to 3*t cycle using the ra[7:6] field. the lrr0, lrr1, and lrr2 commands load the refh/m/l registers from the ra[7:0] field. the refh/m/l registers are also referred to as the refr reg- isters. note that only the bits that are needed for specifying the refresh row (12 bits in all) are implemented in the refr regis- ters ? the rest are reserved. note also that the ra2..0 field that table 3 op field encoding summary op [3:0] packet command description 0000 - nop no operation. 0001 col rd column read (wrx=0). column c9..4 of sense amp in bank bc2. .0 is read to dq bus after delc*t cycle . wr column write (wrx=1). write dq bus to column c9..4 of sense amp in ba nk bc2..0 after delc*t cycle . 0010 colx caly xop3..0 specifies a calibrate or powerdown command ? see table 6 on page 13. 0011 rowp prex pop2..0 specifies a row precharge command ? see table 5 on page 13. refy,lrrr rop2..0 specifies a row refresh command or load refr register comman d ? see table 4 on page 12. 01xx rowa act row activate command. row r11..0 of bank ba2..0 is placed into the sense amp of the bank after dela*t cycle . 1xxx colm wrm column write command (masked) ? ma sk m7..0 specifies which bytes are written. table 4 rop field encoding summary rop[2:0] command description 000 nopr no operation 001 refp refresh precharge command. bank ra2..0 is precharged. this command is delayed by {0,1,2,3}*t cycle (the value is given by the expression (2*ra[7]+ra[6]). 010 refa refresh activate command. row r[11:0] (from refh/m/l register) of bank ra2..0 is placed into sense amp. this command is delayed by {0,1,2,3}*t cycle (the value is given by the expression (2*ra[7]+ra[6]). 011 refi refresh activate command. row r[11:0] (from refh/m/l register) of bank ra2..0 is placed into sense amp. this command is delayed by {0,1,2,3}*t cycle (the value is given by the expression (2*ra[7]+ra[6]). r[11:0] field of refh/m/l register is increm ented after the activate command has completed. 100 lrr0 load refresh low row register (refl). ra[7:0] is stored in r[7:0] field. 101 lrr1 load refresh middle row register (refm). ra[3:0] is stored in r[11:8] field. 110 lrr2 load refresh high row regist er ? not used with this device. 111 - reserved
preliminary data sheet e0643e30 (ver. 3.0) 13 edx5116abse specifies the refresh bank address is also referred to as br2..0. see ?refresh transactions? on page 40. table 5 shows the pop field encoding in the rowp packet. the first encoding specifies a nopp (no operation) command. there are four variations of pre (precharge) command. each uses the bp field to specify the bank to be precharged. each also specifies a different delay of up to 3*t cycle using the pop[1:0] field. a precharge command may be specified in addition to a refresh command using the rop field. table 6 shows the xop field encoding in the colx packet. this field encodes the remaining commands. the calc and cale commands perform calibr ation opera- tions to ensure signal integrit y on the channel. see ?calibra- tion transactions? on page 42. the pdn command causes the device to enter a power-down state. see ?power state management? on page 44. table 5 pop field encoding summary pop [2:0] command description 000 nopp no operation. 001 - reserved. 010 - reserved. 011 - reserved. 100 pre0 row precharge command ? bank bp2..0 is precharged. this comma nd is delayed by 0*t cycle . 101 pre1 row precharge command ? bank bp2..0 is precharged. this comma nd is delayed by 1*t cycle . 110 pre2 row precharge command ? bank bp2..0 is precharged. this comma nd is delayed by 2*t cycle . 111 pre3 row precharge command ? bank bp2..0 is precharged. this comma nd is delayed by 3*t cycle . table 6 xop field encoding summary xop [3:0] command command and description xop [3:0] command command and description 0000 - reserved. 1000 calc current calibration command. 0001 - reserved. 1001 calz impe dance calibration command. 0010 - reserved. 1010 cale end calibration command (calc). 0011 - reserved. 1011 - reserved. 0100 - reserved. 1100 pdn enter powerdown power state. 0101 - reserved. 1101 - reserved. 0110 - reserved. 1110 - reserved. 0111 - reserved. 1111 - reserved.
preliminary data sheet e0643e30 (ver. 3.0) 14 edx5116abse request packet interactions a summary of request packet inte ractions is shown in table 7. each case is limited to request packets with commands that perform memory operations (inc luding refresh commands). this includes all commands in rowa, rowp, col, and colm packets. the commands in colx packets are described in later sections. se e ?maintenance operations? on page 40. request packet/command ?a? is followed by request packet/ command ?b?. the minimum possible spacing between these two packet/commands is 0*t cycle . however, a larger time interval may be needed becaus e of a resource interaction between the two packet/commands. if the minimum possible spacing is 0*t cycle , then an entry of ?no limit? is shown in the table. note that the spacing values shown in the table are relative to the effective beginning of a packet/command. the use of the delay field with a command will delay the position of the effec- tive packet/command from the position of the actual packet/ command. see ?dynamic request scheduling? on page 20. any of the packet/command enco dings under one of the four operation types is equivalent in terms of the resource con- straints. therefore, both the horizontal columns (packet ?a?) and vertical rows (packet ?b?) of the interaction table are divided into four major groups. the four possible operation type s for request packets a and b include: ; [a] activate row ? rowa/act ?rowp/refa ?rowp/refi ; [r] read column ? col/rd ; [w] write column ? col/wr ?colm/wrm ; [p] precharge row ? rowp/pre ?rowp/refp table 7 packet interaction summary second packet/command to bank bb activate row [a] read column [r] wri te column [w] precharge row [p] first packet/command to bank ba rowa - act bb rowp - refa bb rowp - refi bb col - rd bb col - wr bb colm - wrm bb rowp - pre bb rowp - refp bb activate row [a] rowa - act ba rowp - refa ba rowp - refi ba ba,bb different case aad: t rr case ard: no limit case aw d: no limit case apd: no limit ba,bb same case aas: t rc case ars: t rcd-r case aws: t rcd-w case aps: t ras read column [r] col - rd ba ba,bb different case rad: no limit case rrd: t cc case rwd: a t ? rw case rpd: no limit ba,bb same case ras: b t rdp +t rp case rrs: t cc case rws: a t ? rw case rps: t rdp write column [w] col - wr ba colm - wrm ba ba,bb different case wad: no limit case wrd c t ? wr case wwd: t cc case wpd: no limit ba,bb same case was b : t wrp +t rp case wrs: c t ? wr case wws: t cc case wps: t wrp precharge row [p] rowp - pre ba rowp - refp ba ba,bb different case pad: no limit case prd: no limit case pwd: no limit case ppd: t pp ba,bb same case pas: t rp case prs: d t rp +t rcd-r case pws: d t rp +t rcd-w case pps: t rc see examples: figure 4 figure 5 figure 6 figure 7 a. t ? rw is equal to t cc + t rw-bub,xdrdram + t cac - t cwd and is defined in table 17. this also depend s upon propagation delay - see ?propagation delay? on page 28. b. a pre command is needed between the rd and act/re fa commands or the wr/wrm and act/refa commands. c. t ? wr is defined in table 17. d. an act command is needed between the pre/refp an d rd commands or the pre/refp and wr/wrm commands.
preliminary data sheet e0643e30 (ver. 3.0) 15 edx5116abse the first request is shown along th e vertical axis on the left of the table. the second request is shown along the horizontal axis at the top of the table. ea ch request includes a bank speci- fication ?ba? and ?bb?. the firs t and second banks may be the same, or they may be different. these two subcases for each interaction are shown along th e vertical axis on the left. there are 32 possible interaction cases altogether. the table gives each case a label of the form ?xyz?, where ?x? and ?y? are one of the four operation types (?a? for activate, ?r? for read, ?w? for write, or ?p? for precharge) for the first and second request, respectively, and ?z? indicates the same bank (?s?) or different bank (?d?). along the horizontal axis at th e bottom of the table are cross references to four figures (figure 4 through figure 7). each figure illustrates the eight cases in the corresponding vertical column. thus, figure 4 shows the eight cases when the second request is an activate operation (?a?). in the following discus- sion of the cases, only those in which the interaction interval is greater than t cycle will be described. request interaction cases in figure 4, the interaction interval for the aad case is t rr . this parameter is the row-to-row time and is the minimum interval between activate commands to different banks of a device. the interaction interval for the aas case is t rc . this is the row cycle time parameter and is the minimum interval between activate commands to same ba nks of a device. a precharge operation must be in serted between the two activate opera- tions. the interaction interval for the ras case is t rdp + t rp . a pre- charge operation must be insert ed between the read and acti- vate operation. the minimum in terval between a read and a precharge operation to a bank is t rdp . the minimum interval between a precharge and an activate operation to a bank is t rp . the interaction interval for the was case is t wdp + t rp . a precharge operation must be inse rted between the read and the activate operation.the minimum in terval between a write and a precharge operation to a bank is t wdp . the minimum interval between a precharge and an activate operation to a bank is t rp . the interaction interval for the pas case is t rp . the minimum interval between a precharge an d an activate operation to a bank is t rp . in figure 5, the interaction interval for the ars case is t rcd-r . this is the row-to-column-read time parameter and represents the minimum interval between an activate operation and a read operation to a bank. the interaction interval for the rrd and rrs cases is t cc . this is the column-to-column time parameter and represents the minimum interval betwee n two read operations. the interaction interval for the wrd and wrs cases is t ? wr . this is the write-to-read time parameter and represents the minimum interval between a writ e and a read ope ration to any banks. see ?read/write interaction? on page 28. the interaction interval for the prs case is t rp + t rcd-r . an activate operation must be inse rted between the precharge and the read operation. the minimum interval between a precharge and an activate operation to a bank is t rp . the minimum inter- val between an activate and read operation to a bank is t rcd-r . in figure 6, the interaction interval for the aws case is t rcd-w . this is the row-to-column-write timing parameter and repre- sents the minimum interval betw een an activate operation and a write operation to a bank. the interaction interval for the rwd and rws cases is t ? rw . this is the read-to-write time parameter and represents the minimum interval between a read and a write operation to any banks. see ?read/write interaction? on page 28. the interaction interval for the wwd and wws cases is t cc . this is the column-to-column time parameter and represents the minimum interval between two write operations. the interaction interval for the pws case is t rp + t rcd-w . an activate operation must be inse rted between the precharge and the write operation. the mini mum interval between a pre- charge and an activate operation to a bank is t rp . the mini- mum interval between an activate and a write operation to a bank is t rcd-w . in figure 7, the interaction interval for the aps case is t ras . this parameter is the minimum activate-to-precharge time to a bank. the interaction intervals for the rps and wps cases are t rdp and t wdp , respectively. these are the read- or write-to-pre- charge time parameters to a bank. the interaction interval for the ppd case is t pp . this parameter is the precharge-to-precharge time and the minimum interval between precharge commands to different banks of a device. the interaction interval for the pps case is t rc . this is the row cycle time parameter and the minimum interval between pre- charge commands to same banks of a device. an activate oper- ation must be inserted between the two activate operations. this activate operation mu st be placed a time t rp after the first, and a time t ras before the second precharge.
preliminary data sheet e0643e30 (ver. 3.0) 16 edx5116abse figure 4 act-, rd-, wr-, pre-to-act packet interactions t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 a: rowa packet with act,ba,ra t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 aad case (activate-activate-different bank) aas case (activate-activate-same bank) rad case (read-activate-different bank) ras case (read-activate-same bank) wad case (write-activate-different bank) was case (write-activate-same bank) pad case (precharge-activate-different bank) pas case (precharge-activate-same bank) b: rowa packet with act,bb,rb ba bb a: rowa packet with act,ba,ra b: rowa packet with act,bb,rb ba = bb a: col packet with rd,ba,ca b: rowa packet with act,bb,rb ba bb a: col packet with rd,ba,ca b: rowa packet with act,bb,rb ba = bb a: col packet with wr,ba,ca b: rowa packet with act,bb,rb ba bb a: col packet with wr,ba,ca b: rowa packet with act,bb,rb ba = bb a: rowp packet with pre,ba b: rowa packet with act,bb,rb ba bb a: rowp packet with pre,ba b: rowa packet with act,bb,rb ba = bb no limit a pre b act no limit a wr b act no limit a rd b act t rr b act t rc a act t ras t rp a act b act a pre t rdp +t rp t rdp t rp a rd b act a pre t wrp +t rp t wrp t rp a wr b act a pre t rp a pre b act = / = / = / = / dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0
preliminary data sheet e0643e30 (ver. 3.0) 17 edx5116abse figure 5 act-, rd-, wr-, pre-to-rd packet interactions t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 a: rowa packet with act,ba,ra t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 ard case (activate-read different bank) ars case (activate-read same bank) rrd case (read-read different bank) rrs case (read-read same bank) wrd case (write-read different bank) wrs case (write-read same bank) prd case (precharge-read different bank) prs case (precharge-read same bank) b: col packet with rd,bb,cb ba bb a: rowa packet with act,ba,ra b: col packet with rd,bb,cb ba = bb a: col packet with rd,ba,ca b: col packet with rd,bb,cb ba bb a: col packet with rd,ba,ca b: col packet with rd,bb,cb ba = bb a: col packet with wr,ba,ca b: col packet with rd,bb,cb ba bb a: col packet with wr,ba,ca b: col packet with rd,bb,cb ba = bb a: rowp packet with pre,ba b: col packet with rd,bb,cb ba bb a: rowp packet with pre,ba b: col packet with rd,bb,cb ba = bb no limit a pre b rd no limit a act b rd t rp +t rcd-r t rp t rcd-r a pre b rd b act t rcd-r a act b rd t cc b rd a rd t ? wr b rd a wr t ? wr b rd a wr t cc b rd a rd = / = / = / = / dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0
preliminary data sheet e0643e30 (ver. 3.0) 18 edx5116abse figure 6 act-, rd-, wr-, pre-to-wr packet interactions t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 a: rowa packet with act,ba,ra t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 awd case (activate-write different bank) aws case (activate-write same bank) rwd case (read-write-different bank) rws case (read-write-same bank) wwd case (write-write different bank) wws case (write-write same bank) pwd case (precharge-write different bank) pws case (precharge-write same bank) b: col packet with wr,bb,cb ba bb a: rowa packet with act,ba,ra b: col packet with wr,bb,cb ba = bb a: col packet with rd,ba,ca b: col packet with wr,bb,cb ba bb a: col packet with rd,ba,ca b: col packet with wr,bb,cb ba = bb a: col packet with wr,ba,ca b: col packet with wr,bb,cb ba bb a: cop packet with wr,ba,ca b: col packet with wr,bb,cb ba = bb a: rowp packet with prr,ba b: col packet with wr,bb,cb ba bb a: rowp packet with pre,ba b: cop packet with wr,bb,cb ba = bb no limit a pre b wr no limit a act b wr t rp +t rcd-w t rp a pre b wr b act t rcd-w a act b wr t ? rw t cc b wr a wr t cc b wr a wr t cac d(b) q(a) t cwd t cycle a rd b wr t ? rw t cac d(b) q(a) t cwd t cycle a rd b wr = / = / = / = / dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..d0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 t cc t cc t rcd-w
preliminary data sheet e0643e30 (ver. 3.0) 19 edx5116abse figure 7 act-, rd, wr-, pre-to-pre packet interactions t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 a: rowa packet with act,ba,ra t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 t 0 t 1 t 2 t 3 cfm rq11..0 dq15..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn dqn15..0 apd case (activate-precharge different bank) aps case (activate-precharge same bank) rpd case (read-precharge different bank) rps case (read-precharge same bank) wpd case (write-precharge different bank) wps case (write-precharge same bank) ppd case (precharge-precharge different bank) pps case (precharge-precharge same bank) b: rowp packet with pre,bb ba # bb a: rowa packet with act,ba,ra b: rowp packet with prr,bb ba = bb a: col packet with rd,ba,ca b: rowp packet with pre,bb ba # bb a: col packet with rd,ba,ca b: rowp packet with prr,bb ba = bb a: col packet with wr,ba,ca b: rowp packet with pre,bb ba # bb a: col packet with wr,ba,ca b: rowp packet with pre,bb ba = bb a: rowp packet with pre,ba b: rowp packet with pre,bb ba # bb a: rowp packet with pre,ba b: rowp packet with pre,bb ba = bb no limit a wr b pre no limit a rd b pre t rc t rp t ras a pre b pre b act no limit a act b pre t pp b pre a pre t ras b pre a act t rdp b pre a rd t wrp b pre a wr dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0
preliminary data sheet e0643e30 (ver. 3.0) 20 edx5116abse dynamic request scheduling delay fields are present in the rowa, col, and rowp pack- ets. they permit the associated command to optionally wait for a time of one (or more) t cycle before taking effect. this allows a memory controller more scheduling flexibility when issuing request packets. figure 8 illustrates the use of the delay fields. in the first timing diagram, a rowa packet with an act com- mand is present at cycle t 0 . the dela field is set to ?1?. this request packet will be equivalent to a rowa packet with an act command at cycle t 1 with the dela field is set to ?0?. this equivalence should be used when analyzing request packet interactions. in the second timing diagram, a col packet with a rd com- mand is present at cycle t 0 . the delc field is set to ?1?. this request packet will be equivalent to a col packet with an rd command at cycle t 1 with the delc field is set to ?0?. this equivalence should be used wh en analyzing request packet interactions. in a similar fashion, a col packet with a wr command is present at cycle t 12 . the delc field is set to ?1?. this request packet will be equivalent to a col packet with a wr com- mand at cycle t 13 with the delc field is set to ?0?. this equivalence should be used wh en analyzing request packet interactions. in the col packet with a rd command example, the read data delay t cac is measured between the q read data packet and the virtual col packet at cycle t 1 . likewise, for the example with the col packet with a wr command, the write data delay t cwd is measured between the d write data packet and the virtual col packet at cycle t 13 . in the third timing diagram, a rowp packet with a pre com- mand is present at cycle t 0 . the del field (pop[1:0]) is set to ?11?. this request packet will be equivalent to a rowp packet with a pre command at cycle t 1 with the del field is set to ?10?, it will be equivalent to a rowp packet with a pre com- mand at cycle t 2 with the del field is set to ?01?, and it will be equivalent to a rowp packet with a pre command at cycle t 3 with the del field is set to ?00?. this equivalence should be used when analyzing re quest packet interactions. in the fourth timing diagram, a rowp packet with a refp command is present at cycle t 0 . the del field (ra[7:6]) is set to ?11?. this request packet will be equivalent to a rowp packet with a refp command at cycle t 1 with the del field is set to ?10?, it will be equivalent to a rowp packet with a refp command at cycle t 2 with the del field is set to ?01?, and it will be equivalent to a rowp packet with a refp com- mand at cycle t 3 with the del field is set to ?00?. this equiv- alence should be used when analyzing request packet interactions. the two examples for the refa and refi commands are identical to the example just described for the refp com- mand. the rowp packet allows two independent operations to be specified. a pre precharge command uses the pop and bp fields, and the refp, refa, or refi commands uses the rop and ra fields. both operations have an optional delay field (the pop field for the pre command and the ra field with the refp, refa, or refi commands). the two delay mechanisms are independent of one another. the pop field does not affect the timing of the refp, refa, or refi com- mands, and the ra field does not affect the timing of the pre command. when the interactions of a rowp packet are analyzed, it must be remembered that there are two independent commands specified, both of which may af fect how soon the next request packet can be issued. the cons traints from both commands in a rowp packet must be consider ed, and the one that requires the longer time interval to the next request packet must be used by the memory controlle r. furthermore, the two com- mands within a rowp packet may not reference the same bank in the bp and ra fields.
preliminary data sheet e0643e30 (ver. 3.0) 21 edx5116abse figure 8 request scheduling examples t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cycle t cac t cycle del0 act q t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cycle rowa/act command col/rd and col/wr commands rowp/pre command del0 rd t cwd d del0 wr del1 act del1 rd del1 wr del2 pre del3 pre del0 pre del1 pre act w/del=1 at t 0 is equivalent to act w/del=0 at t 1 rd w/del=1 at t 0 is equivalent to rd w/del=0 at t 1 wr w/del=1 at t 12 is equivalent to wr w/del=0 at t 13 pre w/del=3 at t 0 is equivalent to pre w/del =2 at t 1 or pre w/del=1 at t 2 or pre w/del=0 at t 3 note del value is specified by {pop1, pop0} field. dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cycle rowp/refp,refa,refi commands del2 refp del3 refp del0 refp del1 refp refp w/del=3 at t 0 is equivalent to refp w/del=2 at t 1 or refp w/del=1 at t 2 or refp w/del=0 at t 3 note del value is specified by {ra7, ra6} field. dq15..0 dqn15..0 cfm cfmn rq11..0 del2 refi del3 refi del0 refi del1 refi refi w/del=3 at t 13 is equivalent to refi w/del=2 at t 14 or refi w/del=1 at t 15 or refi w/del=0 at t 16 del2 refa del3 refa del0 refa del1 refa at t 7 or refa w/del=1 at t 8 or refa w/del=0 at t 9 refa w/del=3 at t 6 is equivalent to refa w/del=2 note del value is specified by dela field. note del value is specified by delc field.
preliminary data sheet e0643e30 (ver. 3.0) 22 edx5116abse memory operations write transactions figure 9 shows four examples of memory write transactions. a transaction is one or more requ est packets (and the associated data packets) needed to perfor m a memory access. the state of the memory core and the address of the memory access deter- mine how many request packets are needed to perform the access. the first timing diagram shows a page-hit write transaction. in this case, the selected bank is already open (a row is already present in the sense amp array for the bank). in addition, the selected row for the memory ac cess matches the address of the row already sensed (a page hit). this comparison must be done in the memory controller. in this example, the access is made to row ra of bank ba. in this case, write data may be directly written into the sense amp array for the bank, and ro w operations (activate or pre- charge) are not needed. a col packet with wr command to column ca1 of bank ba is presented on edge t 0 , and a second col packet with wr command to column ca1 of bank ba is presented on edge t 2 . two write data packets d(a1) and d(a2) follow these col packets after the write data delay t cwd . the two col packets are separated by the column-cycle time t cc . this is also the length of each write data packet. the second timing diagram show s an example of a page-miss write transaction. in this case, the selected bank is already open (a row is already present in the sense amp array for the bank). however, the selected row for the memory access does not match the address of the row alread y sensed (a page miss). this comparison must be done in the memory controller. in this example, the access is made to row ra of bank ba, and the bank contains a row other than ra. in this case, write data may be not be directly written into the sense amp array for the bank. it is necessary to close the present row (precharge) and access the requested row (acti- vate). a precharge command (pre to bank ba) is presented on edge t 0 . an activate command (act to row ra of bank ba) is presented on edge t 6 a time t rp later. a col packet with wr command to column ca1 of bank ba is presented on edge t 7 a time t rcd-w later. a second col packet with wr command to column ca2 of bank ba is presented on edge t 9 . two write data packets d(a1) and d(a2) follow these col packets after the write data delay t cwd . the two col packets are separated by the column-cycle time t cc . this is also the length of each write data packet. the third timing diagram shows an example of a page-empty write transaction. in this case, the selected bank is already closed (no row is present in the sense amp array for the bank). no row comparison is necessary for this case; however, the memory controller must still remember that bank ba has been left closed. in this example, the access is made to row ra of bank ba. in this case, write data may be not be directly written into the sense amp array for the bank. it is necessary to access the requested row (activate). an activate command (act to row ra of bank ba) is presented on edge t 0 . a col packet with wr command to column ca1 of bank ba is presented on edge t 1 a time t rcd-w later. a second col packet with wr com- mand to column ca2 of bank ba is presented on edge t 3 . two write data packets d(a1) and d(a2) follow these col packets after the write data delay t cwd . the two col packets are sepa- rated by the column-cycle time t cc . this is also the length of each write data packet. after the final write command, it may be necessary to close the presen t row (precharge). a precharge command (pre to bank ba) is presented on edge t 14 a time t wrp after the last col packet with a wr command. the decision whether to close the bank or leave it open is made by the memory controller and its page policy. the fourth timing diagram show s another example of a page- empty write transaction. this is similar to the previous example except that only a single write command is presented, rather than two write commands. this example shows that even with a minimum length writ e transaction, the t ras parameter will not be a constraint. the t ras measures the minimum time between an activate command and a precharge command to a bank. this time interval is also constrained by the sum t rcd- w +t wrp which will be larger for a write transaction. these two constraints ( t ras and t rcd-w +t wrp ) will be a function of the memory device?s speed bin and the data transfer length (the number of write commands issued between the activate and precharge commands), and the t ras parameter could become a constraint for write transactions for future speed bins. in this example, the sum t rcd-w +t wrp is greater than t ras by the amount ? t ras .
preliminary data sheet e0643e30 (ver. 3.0) 23 edx5116abse figure 9 write transactions t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cc t cwd t cycle transaction a: wr a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cc t cwd t cycle t rp t rcd-w a1 wr a2 wr a1 wr a2 wr a3 pre a0 act d(a2) d(a1) d(a2) d(a1) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: wr a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cc t cwd t cycle t wrp t rcd-w a1 wr a2 wr a3 pre a0 act d(a2) d(a1) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: wr a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cwd t cycle t rcd-w a1 wr a3 pre a0 act d(a1) t ras transaction b: wr b0 = {bb,rb} b1 = {bb,cb1} b2 = {bb,cb2} b3 = {bb} bb = ba b0 act t rp page-hit write example page-miss write example page-empty write example page-empty write exam ple - core limited dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 t wrp ? t ras t cwd t dp
preliminary data sheet e0643e30 (ver. 3.0) 24 edx5116abse read transactions figure 10 shows four examples of memory read transactions. a transaction is one or more re quest packets (and the associ- ated data packets) needed to perform a memory access. the state of the memory core and the address of the memory access determine how many request packets are needed to per- form the access. the first timing diagram shows a page-hit read transaction. in this case, the selected bank is already open (a row is already present in the sense amp array for the bank). in addition, the selected row for the memory ac cess matches the address of the row already sensed (a page hit). this comparison must be done in the memory controller. in this example, the access is made to row ra of bank ba. in this case, read data may be directly read fr om the sense amp array for the bank, and no row operations (activate or pre- charge) are needed. a col packet with rd command to col- umn ca1 of bank ba is presented on edge t 0 , and a second col packet with rd command to column ca2 of bank ba is presented on edge t 2 . two read data packets q(a1) and q(a2) follow these col packets after the read data delay t cac . the two col packets are separated by the column-cycle time t cc . this is also the length of each read data packet. the second timing diagram show s an example of a page-miss read transaction. in this case, th e selected bank is already open (a row is already present in the sense amp array for the bank). however, the selected row for the memory access does not match the address of the row alread y sensed (a page miss). this comparison must be done in the memory controller. in this example, the access is made to row ra of bank ba, and the bank contains a row other than ra. in this case, read data may not be directly read from the sense amp array for the bank. it is necessary to close the present row (precharge) and access the requested row (activate). a pre- charge command (pre to bank ba) is presented on edge t 0 . an activate command (act to row ra of bank ba) is pre- sented on edge t 6 a time t rp later. a col packet with rd command to column ca1 of bank ba is presented on edge t 11 a time t rcd-r later. a second col packet with rd command to column ca2 of bank ba is presented on edge t 13 . two read data packets q(a1) and q(a2) follow these col packets after the read data delay t cac . the two col packets are separated by the column-cycle time t cc . this is also the length of each read data packet. the third timing diagram shows an example of a page-empty write transaction. in this case, the selected bank is already closed (no row is present in the sense amp array for the bank). no row comparison is necessary for this case; however, the memory controller must still remember that bank ba has been left closed. in this example, the access is made to row ra of bank ba. in this case, read data may not be directly read from the sense amp array for the bank. it is necessary to access the requested row (activate). an activate command (act to row ra of bank ba) is presented on edge t 0 . a col packet with rd com- mand to column ca1 of bank ba is presented on edge t 5 a time t rcd-r later. a second col packet with rd command to column ca2 of bank ba is presented on edge t 7 . two read data packets q(a1) and q(a2) follow these col packets after the read data delay t cac . the two col packets are separated by the column-cycle time t cc . this is also the length of each read data packet. after the final read command, it may be necessary to close the present row (precharge). a precharge command ? pre to bank ba ? is presented on edge t 10 a time t rdp after the last col packet with a rd command. whether the bank is closed or left open depends on the memory controller and its page policy. the fourth timing diagram show s another example of a page- empty read transaction. this is similar to the previous example except that it uses one read command instead of two read com- mands. in this case, the core parameter t ras may also be a con- straint upon when the precharge command may be issued. the t ras measures the minimum time between an activate command and a precharge command to a bank. this time interval is also constrained by the sum t rcd-r + t rdp and must be set to whichever is larger. these two constraints (t ras and t rcd-r + t rdp ) will be a function of the memory device?s speed bin and the data transfer leng th (the number of read com- mands issued between the activate and precharge commands). in this example, the t ras is greater than the sum t rcd-r + t rdp by the amount ? t rdp .
preliminary data sheet e0643e30 (ver. 3.0) 25 edx5116abse figure 10 read transactions t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: rd a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cc t cac t cycle transaction a: rd a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cc t cac t cycle t rp t rcd-r a1 rd a2 rd a1 rd a2 rd a3 pre a0 act q(a2) q(a1) q(a2) q(a1) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: rd a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cc t cac t cycle t rdp t rcd-r a1 rd a2 rd a3 pre a0 act q(a2) q(a1) t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: rd a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} t cac t cycle t rcd-r a1 rd a3 pre a0 act q(a1) t ras transaction b: rd b0 = {bb,rb} b1 = {bb,cb1} b2 = {bb,cb2} b3 = {bb} bb = ba b0 act t rp page-hit read example page-miss read example page-empty read example page-empty read exam ple - core limited dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 t rdp ? t rdp
preliminary data sheet e0643e30 (ver. 3.0) 26 edx5116abse interleaved transactions figure 11 shows two examples of interleaved transactions. interleaved transactions are ov erlapped with one another; a transaction is started before an earlier one is completed. the timing diagram at the top of the figure shows interleaved write transactions. each transaction assumes a page-empty access; that is, a bank is in a closed state prior to an access, and is precharged after the access. with this assumption, each transaction requires the same nu mber of request packets at the same relative positions. if banks were allowed to be in an open state, then each transaction would require a different number of request packets depending upon whether th e transaction was page-empty, page-hit, or page-miss. this situation is more complicated for the memory controller, and will not be ana- lyzed in this document. in the interleaved page-empty write example, there are four sets of request pins rq11..0 sh own along the left side of the timing diagram. the first three show the timing slots used by each of the three request packet types (act, col, and pre), and the fourth set (all) shows the previous three merged together. this allows the pattern used for allocating request slots for the different packet s to be seen more clearly. the slots at {t 0 , t 4 , t 8 , t 12 , ...} are used for rowa packets with act commands. this spacing is determined by the t rr parameter. there should not be interference between the inter- leaved transactions due to resour ce conflicts because each bank address ? ba, bb, bc, bd, and be ? is assumed to be differ- ent from another. if two of th e bank addresses are the same, the later transaction would need to wait until the earlier trans- action had completed its precharg e operation. five different banks are needed because the effective t rc (t rc + ? t rc ) is 20*t cycle . the slots at {t 1 , t 3 , t 5 , t 7 , t 9 , t 11 , ...} are used for col packets with wr commands. this frequency of the col packet spacing is determined by the t cc parameter and by the fact that there are two column accesses per row access. the phasing of the col packet spacing is determined by the t rcd- w parameter. if the value of t rcd-w required the col packets to occupy the same request slots as the rowa packets (this case is not shown), the delc field in the col packet could be used to place the col packet one t cycle earlier. the dq bus slots at {t 7 , t 9 , t 11 , t 13 , ...} carry the write data packets {d(a1), d(a2), d(b1), d(b2 ), ....}. two write data pack- ets are written to a bank in ea ch transaction. the dq bus is completely filled with write data; no idle cycles need to be introduced because there are no resource conflicts in this example. the slots at {t 14 , t 18 , t 22 , ...} are used for rowp packets with pre commands. this frequency of rowp packet spac- ing is determined by the t pp parameter. the phasing of the rowp packet spacing is determined by the t wrp parameter. if the value of t wrp required the rowp packets to occupy the same request slots as the rowa or col packets already assigned (this case is not shown), the delay field in the rowp packet could be used to place the rowp packet one or more t cycle s earlier. there is an example of an interleaved page-empty read at the bottom of the figure. as before, there are four sets of request pins rq11..0 shown along the left side of the timing diagram, allowing the pattern used for al locating request slots for the different packets to be seen more clearly. the slots at {t 0 , t 4 , t 8 , t 12 , ...} are used for rowa packets with act commands. this spacing is determined by the t rr parameter. there should not be interference between the inter- leaved transactions due to resour ce conflicts because each bank address ? ba, bb, bc, and bd ? is assumed to be different from another. four different banks are needed because the effective t rc is 16*t cycle . the slots at {t 5 , t 7 , t 9 , t 11 , ...} are used for col packets with rd commands. this frequency of the col packet spac- ing is determined by the t cc parameter and by the fact that there are two column accesses per row access. the phasing of the col packet spacing is determined by the t rcd-r parame- ter. if the value of t rcd-r required the col packets to occupy the same request slots as the ro wa packets (this case is not shown), the delc field in the col packet could be used to place the packet one t cycle earlier. the dq bus slots at {t 11 , t 13 , t 15 , t 17 , ...} carry the read data packets {q(a1), q(a2), q(b1), q(b2), ...}. two read data pack- ets are read from a bank in ea ch transaction. the dq bus is completely filled with read data ? that is, no idle cycles need to be introduced because there are no resource conflicts in this example. the slots at {t 10 , t 14 , t 18 , t 22 , ...} are used for rowp pack- ets with pre commands. this frequency of the rowp packet spacing is determined by the t pp parameter. the phasing of the rowp packet spacing is determined by the t rdp parameter. if the value of t rdp required the rowp packets to occupy the same request slots as the rowa or col packets already assigned (this case is not shown), the delay field in the rowp packet could be used to place the rowp packet one or more t cycle s earlier.
preliminary data sheet e0643e30 (ver. 3.0) 27 edx5116abse figure 11 interleaved transactions t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: wr a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} transaction b: wr b0 = {bb,rb} b1 = {bb,cb1} b2 = {bb,cb2} b3 = {bb} transaction c: wr c0 = {bc,rc} c1 = {bc,cc1} c2 = {bc,cc2} c3 = {bc} transaction d: wr d0 = {bd,rd} d1 = {bd,cd1} d2 = {bd,cd2} d3 = {bd} transaction e: wr e0 = {be,re} e1 = {be,ce1} e2 = {be,ce2} e3 = {be} bf = ba are different ba,bb,bc,bd,be d(a2) d(a1) d(b2) d(b1) d(c2) transaction a: rd a0 = {ba,ra} a1 = {ba,ca1} a2 = {ba,ca2} a3 = {ba} transaction b: rd b0 = {bb,rb} b1 = {bb,cb1} b2 = {bb,cb2} b3 = {bb} transaction c: rd c0 = {bc,rc} c1 = {bc,cc1} c2 = {bc,cc2} c3 = {bc} transaction d: rd d0 = {bd,rd} d1 = {bd,cd1} d2 = {bd,cd2} d3 = {bd} transaction e: rd e0 = {be,re} e1 = {be,ce1} e2 = {be,ce2} e3 = {be} be = ba different banks. ba,bb,bc,bd are interleaved page-empty write example interleaved page-empty read example transaction f: wr f0 = {bf,rf} f1 = {bf,cf1} f2 = {bf,cf2} f3 = {bf} banks. c0 act d0 act a0 act b0 act e0 act b1 wr b2 wr c1 wr c2 wr d1 wr d2 wr e1 wr e2 wr t rc t rcd-w a1 wr b1 wr b2 wr c1 wr c2 wr c0 act d1 wr d2 wr d0 act e1 wr e2 wr a2 wr a3 pre a0 act b3 pre b0 act c3 pre e0 act f0 act b3 pre c3 pre t cc t wrp t cwd a1 wr a2 wr a3 pre t rp t rr d(c1) ? t rc t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 c0 act d0 act a0 act b0 act e0 act f0 act b1 rd b2 rd c1 rd c2 rd d1 rd d2 rd e1 rd e2 rd t rc t rcd-r a1 rd b1 rd b2 rd c1 rd c2 rd c0 act d1 rd d2 rd d0 act e1 rd e2 rd a2 rd a3 pre a0 act b3 pre b0 act d3 pre e0 act f0 act t cc t rdp t cac a1 rd a2 rd t rp t rr c3 pre t cycle t cycle the effective t rc time is increased by 4 t cycle dq15..0 dqn15..0 cfm cfmn rq11..0 (act) rq11..0 (col) rq11..0 (pre) rq11..0 (all) dq15..0 dqn15..0 cfm cfmn rq11..0 (act) rq11..0 (col) rq11..0 (pre) rq11..0 (all) q(a2) q(a1) q(b2) q(b1) q(c2) q(c1) d(d2) d(e1) f1 wr f2 wr d(d1) f0 act f1 wr f2 wr a3 pre b3 pre d3 pre c3 pre d(e1) ? t wrp
preliminary data sheet e0643e30 (ver. 3.0) 28 edx5116abse read/write interaction the previous section described overlapped read transactions and overlapped write transactions in isolation. this section will describe the interaction of read and write transactions and the spacing required to avoid channe l and core resource conflicts. figure 12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. two col packets with wr commands are presented on cycles t 0 and t 2 . the write data packets are presented a time t cwd later on cycles t 4 and t 6 . the device requires a time t ? wr after the sec- ond col packet with a wr command before a col packet with a rd command may be presented. two col packets with rd commands are presented on cycles t 11 and t 13 . the read data packets are returned a time t cac later on cycles t 17 and t 19 . the time t ? wr is required for turn ing around internal bidirectional interconnections (i nside the device). this time must be observed regardless of whether the write and read commands are directed to the sa me bank or different banks. a gap t wr-bub,xdrdram will appear on the dq bus between the end of the d(a2) packet and the beginning of the q(b1) packet (measured at the appr opriate packet reference points). the size of this gap can be evaluated by calculating the difference between cycles t 2 and t 17 using the two timing paths: t wr-bub,xdrdram t ? wr + t cac - t cwd - t cc in this example, the value of t wr-bub,xdrdram is greater than its minimum value of t wr-bub,xdrdram,min . the values of t ? rw and t cac are equal to their minimum values. in the second case, the timing diagram displayed at the bottom of figure 12 illustrates a read transaction followed by a write transaction. two co l packets with rd commands are pre- sented on cycles t 0 and t 2 . the read data packets are returned a time t cac later on cycles t 6 and t 8 . the device requires a time t ? rw after the second col packet with a rd command before a col packet with a wr command may be presented. two col packets with wr commands are presented on cycles t 10 and t 12 . the write data packets are presented a time t cwd later on cycles t 13 and t 15 . the time t ? rw is required for turn- ing around the external dq bidirectional interconnections (outside the device). this ti me must be observed regardless whether the read and write commands are directed to the same bank or different banks. the time t ? rw depends upon four timing parameters, and may be evaluated by calculating the dif- ference between cycles t 2 and t 13 using the two timing paths: t ? rw + t cwd = t cac + t cc + t rw-bub,xdrdram or t ? rw = (t cac - t cwd )+ t cc + t rw-bub,xdrdram in this example, the values of t ? rw , t cac , t cwd , t cc , and t rw- bub,xdrdram are equal to their minimum values. propagation delay figure 13 shows two timing diagrams that display the system- level timing relations hips between the memory component and the memory controller. the timing diagram at the top of the figure shows the case of a write-read-write command and data at the memory compo- nent. in this case, the timing will be identical to what has already been shown in the previous sections; i.e. with all timing measured at the pins of the memory component. this timing diagram was produced by merging portions of the top and bot- tom timing diagrams in figure 12. the example shown is that of a single col packet with a write command, followed by a single col packet with a read com- mand, followed by a second col packet with a write com- mand. these accesses all assume a page-hit to an open bank. a timing interval t ? wr is required between the first wr com- mand and the rd command, and a timing interval t ? rw is required between the rd command and the second wr com- mand. there is a write data delay t cwd between each wr com- mand and the associated write da ta packet d. there is a read data delay t cac between the rd command and the associated read data packet q. in this exam ple, all timing parameters have assumed their minimum values except t wr-bub,xdrdram . the lower timing diagram in the figure shows the case where timing skew is present between the memory controller and the memory component. this skew is the result of the propagation delay of signal wavefronts on the wires carrying the signals. the example in the lower diagram assumes that there is a prop- agation delay of t pd-rq along both the rq wires and the cfm/cfmn clock wires betwee n the memory controller and the memory component (the value of t pd-rq used here is 1*t cycle ). note that in an actual system the t pd-rq value will be different for each memory component connected to the rq wires. in addition, it is assumed that there is a propagation delay t pd- d along the dq/dqn wires betw een the memory controller and the memory component (the direction in which write data travels, and it is assumed that there is the same propagation delay t pd-q along the dq/dqn wires between the memory component and the memory contro ller (the direction in which read data travels). the sum of these two propagation delays is also denoted by the timing parameter t pd,cyc = t pd-d +t pd-q .
preliminary data sheet e0643e30 (ver. 3.0) 29 edx5116abse figure 12 write/read interaction t 0 t 1 t 2 t 3 cfm rq11..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn transaction a: wr a1 = {ba,ca1} a2 = {ba,ca2} transaction b: rd b1 = {bb,cb1} b2 = {bb,cb2} b2 rd t 0 t 1 t 2 t 3 cfm rq11..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn b2 wr d(b2) t cwd q(b2) q(b1) t cac a1 wr t cac a1 rd t cwd b1 wr d(b1) t ? rw d(a2) q(a2) a2 rd d(a1) q(a1) write/read turnaround example read/write turnaround example t cycle t cycle b1 rd a2 wr t ? wr dq15..0 dqn15..0 dq15..0 dqn15..0 t rw-bub, xdrdram t cc t cc t wr-bub, xdrdram t cwd t dr transaction a: wr a1 = {ba,ca1} a2 = {ba,ca2} transaction b: rd b1 = {bb,cb1} b2 = {bb,cb2}
preliminary data sheet e0643e30 (ver. 3.0) 30 edx5116abse as a result of these propagation delays, the position of packets will have timing skews that de pend upon whether they are measured at the pins of the me mory controller or the pins of the memory component. for example, the cfm/cfmn sig- nals at the pins of the memory component are t pd-rq later than at the pins of the memory controller. this is shown by the cycle numbering of the cfm/cfmn signals at the two loca- tions ? in this example cycle t 1 at the memory controller aligns with cycle t 0 at the memory component. all the request packets on the rq wires will have a t pd-rq skew at the memory component relative to the memory con- troller in this example. because the t pd-d propagation delay of write data matches the t pd-rq propagation delay of the write command, the controller may issu e the write data packet d(a0) relative to the col packet with the first write command ?wr a0? with the normal write data delay t cwd . if the propagation delays between the memory controller and memory compo- nent were different for the rq and dq buses (not shown in this example), the write data delay at the memory controller would need to be adjusted. a propagation delay is seen by the read command ? that is, the read command will be delayed by a t pd-rq skew at the memory component relative to the memory controller. the memory component will return th e read data packet q(b0) rel- ative to this read command with the normal read data delay t cac (at the pins of the memory component). the read data packet will be sk ewed by an additional propaga- tion delay of t pd-q as it travels from the memory component back to the memory controller. the effective read data delay measured between the read command and the read data at the memory controller will be t cac +t pd-rq +t pd-q . the t pd-rq factor is caused by the propagation delay of the request packets as they travel from memory controller to mem- ory component. the t pd-q factor is caused by the propagation delay of the read data packets as they travel from memory com- ponent to memory controller. all timing parameters will be equal to their minimum values except t wr-bub,xdrdram (as in the top diagram), and the tim- ing parameters t rw-bub,xdrdram and t ? rw . these will be larger than their minimum values by the amount (t pd,cyc - t pd,cyc,min ), where t pd,cyc = t pd-d +t pd-q . this may be seen by evaluating the two timi ng paths between cycle t 9 at the controller and cycle t 21 at the xdr dram: t ? rw + t pd-rq + t cwd = t pd-rq + t cac + t cc + t rw-bub,xdrdram or t ? rw = (t cac - t cwd )+ t cc + t rw-bub,xdrdram the following relationship was shown for figure 12 t ? rw ,min = (t cac - t cwd )+ t cc + t rw-bub,xdrdram,min or (t ? rw - t ? rw ,min )= (t rw-bub,xdrdram - t rwbub,xdrdram,min ) in other words, the two timing parameters t rw-bub,xdrdram and t ? rw will change together. the relationship of this change to the propagation delay t pd,cyc (= t pd-d +t pd-q ) can be derived by looking at the two timing paths from t15 to t21 at the xdr dram: t pd-q + t cc + t rw-bub,xio + t pd-d = t cc + t rw-bub,xdrdram or t rw-bub,xdrdram = t rw-bub,xio + t pd-d + t pd-q or t rw-bub,xdrdram = t rw-bub,xio + t pd,cyc in a system with minimum propagation delays: t rw-bub,xdrdram,min = t rw-bub,xio + t pd,cyc,min and since t rw-bub,xio is equal to t rw-bub,xio,min in both cases, the following is true: (t pd,cyc - t pd,cyc,min ) = (t rw-bub,xdrdram - t rw-bub,xdrdram,min ) = (t ? rw - t ? rw ,min )= in other words, the values of the t rw-bub,xdrdram,min and t ? rw ,min timing parameters correspond to the value of t pd,cyc,min for the system (this is equal to one t cycle ). as t pd,cyc is increased from this minimum value, t rw- bub,xdrdram and t ? rw increase from their minimum values by an equivalent amount.
preliminary data sheet e0643e30 (ver. 3.0) 31 edx5116abse figure 13 propagation delay t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 8 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: wr a0 = {ba,ca0} transaction c: wr c0 = {bc,cc0} transaction b: rd b0 = {bb,cb0} t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 write-read-write at xdr dram write-read-write at controller and xdr dram t pd-rq a0 wr a0 wr t pd-q t pd-d d(a0) d(a0) c0 wr t cycle t cycle t cycle t ? rw t ? wr b0 rd c0 wr a0 wr t ? wr b0 rd t pd-rq b0 rd t pd-d t cwd t cac d(a0) q(b0) t cwd d(c0) t cwd t cac t cwd c0 wr t pd-rq q(b0) q(b0) d(c0) d(c0) transaction a: wr a0 = {ba,ca0} transaction c: wr c0 = {bc,cc0} transaction b: rd b0 = {bb,cb0} dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 xdr dram controller xdr dram t -1 ... ... controller rq dq t pd-rq t pd-d t pd-q t rw-bub,xio t cc t rw-bub, xdrdram t cc t ? rw w/ t pd-rq = t pd-q = t pd-d = 1*t cycle t rw-bub, xdrdram t wr-bub, xdrdram t cc (portions of top and bottom timing diagrams of figure 12 merged) t cc rq dq xdr dram
preliminary data sheet e0643e30 (ver. 3.0) 32 edx5116abse register operations serial transactions the serial interface consists of five pins. this includes rst, sck, cmd, sdi, and sdo. sdo uses cmos signaling levels. the other four pins use rsl sign aling levels. rst, cmd, sdi, and sdo use a timing window which surrounds the falling edge of sck). the rst pin is used for initialization. figure 14 and figure 15 show exam ples of a serial write trans- action and a serial read transaction. each transaction starts on cycle s 4 and requires 32 sck edges. the next serial transaction can begin on cycle s 36 . sck does not need to be asserted if there is no transaction. serial write transaction the serial device write transacti on in figure 14 begins with the start[3:0] field. this consists of bits ?1100? on the cmd pin. this indicates to the xdr dram that the remaining 28 bits constitute a serial transaction. the next two bits are the scmd[1 :0] field. this field contains the serial command, the bits 00 in the case of a serial device write transaction. the next eight bits are ?00? and the sid[5:0] field. this field contains the serial identificati on of the device being accessed. the next eight bits are the sadr[7 :0] field. this field contains the serial address of the control register being accessed. a single bit ?0? follows next. th is bit allows one cycle for the access time to the control register. the next eight bits on the cmd pi n is the swd[7:0] field. this is the write data that is placed into the selected control register. a final bit ?0? is driven on the cmd pin to finish the serial write transaction. a serial broadcast write is identi cal except that the contents of the sid[5:0] field in the transaction is ignored and all devices preform the register write. the sdi and sdo pins are not used during either serial write transaction. serial read transaction the serial device read transacti on in figure 15 begins with the start[3:0] field. this consists of bits ?1100? on the cmd pin. this indicates that the remainin g 28 bits constitute a serial transaction. the next two bits are the scmd[1 :0] field. this field contains the serial command, and the bits ?10? in the case of a serial device read transaction. the next eight bits are ?00? and the sid[5:0] field. this field contains the serial identificati on of the device being accessed. the next eight bits are the sadr[7:0] field and contain the serial address of the contro l register being accessed. a single bit ?0? follows next. th is bit allows one cycle for the access time to the control register and time to turn on the sdo output driver. the next eight bits on the cmd pin are the sequence ?00000000?. at the same time, the eight bits on the sdo pin are the srd[7:0] field. this is the read data that is accessed from the selected control regist er. note the output timing con- vention here: bit srd[7] is driven from a time t q,si,max after edge s 26 to a time t q,si,min after edge s 27 . the bit is sampled in the controller by the edge s 27 a final bit ?0? is driven on the cmd pin to finish the serial read transaction. a serial forced read is identical except that the contents of the sid[5:0] field in the transaction is ignored and all devices pre- form the register read. this is used for device testing. figure 16 shows the response of a dram to a serial device read transaction when its internal sid[5:0] register field doesn?t match the sid[5:0] field of the tr ansaction. instead of driving read data from an internal register for cycle edges s 27 through s 34 on the sdo output pin, it passes the input data from the sdi input pin to the sdo output pin during this same period. table 8 scmd field encoding summary scmd [1:0] command description 00 sdw serial device write ? one device is wri tten, the one whose sid[5:0] register matc hes the sid[5:0] field of the transaction . 01 sbw serial broadcast write ? all devices are written, regardless of the contents of th e sid[5:0] register and the sid[5:0] tra nsaction field 10 sdr serial device read ? one device is read, the one whose sid[ 5:0] register matches the sid[5:0] field of the transaction. 11 sfr serial forced read ? all de vices are read, regardless of th e contents of the sid[5:0] regi ster and the sid[5:0] transactio n field
preliminary data sheet e0643e30 (ver. 3.0) 33 edx5116abse figure 14 serial write transaction figure 15 serial read transaction ? selected dram figure 16 serial read transaction ? non-selected dram s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 18 s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 36 s 38 s 40 s 42 s 44 s 46 s 16 s 48 2 4 3 5 0 1 ?0? ?0? 2?h0,sid[5:0] ?0? ?0? scmd transaction t cyc,sck ?1? ?1? ?0? ?0? start 2 4 3 5 0 1 6 7 swd[7:0] ?0? ?0? rst sdi (input) sck cmd sdo (output) 2 4 3 5 0 1 6 7 sadr[7:0] s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 18 s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 36 s 38 s 40 s 42 s 44 s 46 s 16 s 48 2 4 3 5 0 1 ?0? ?0? 2?h0,sid[5:0] ?1? ?0? scmd transaction t cyc,sck ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? 8?h00 ?1??1??0??0? start ?0? ?0? rst sdi (input) sck cmd sdo (output) 2 4 3 5 0 1 6 7 sadr[7:0] 2 4 3 5 0 1 6 7 srd[7:0] s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 18 s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 36 s 38 s 40 s 42 s 44 s 46 s 16 s 48 2 4 3 5 0 1 ?0? ?0? 2?h0,sid[5:0] ?1? ?0? scmd transaction t cyc,sck ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? 8?h00 ?1??1??0??0? start ?0? ?0? rst sdi (input) sck cmd sdo (output) 2 4 3 5 0 1 6 7 sadr[7:0] 2 4 3 5 0 1 6 7 srd[7:0] 2 4 3 5 0 1 6 7 srd[7:0] sdi sdo t p, s i s 28 combinational propagation from sdi to sdo
preliminary data sheet e0643e30 (ver. 3.0) 34 edx5116abse register summary figure 17 through figure 33 show the control registers in the memory component. the control registers are responsible for configuring the component?s ope rating mode, for managing power state transitions, for mana ging refresh, and for manag- ing calibration operations. a control register may contain up to eight bits. each figure shows defined bits in white and re served bits in gray. reserved bits must be written as 0 an d must be ignored when read. write-only fields must be ignored when read each figure displays the following register information: 1. register name 2. register mnemonic 3. register address (sadr[7:0] value needed to access it) 4. read-only, write-only or read-write 5. initialization state 6. description of each defined register field figure 17 shows the serial identification register. this register contains the sid[5:0] (serial identification field). this field contains the serial identification value for the device. the value is compared to the sid[5:0] field of a serial transaction to determine if the serial transaction is directed to this device. the serial identification value is set during the initialization sequence. figure 18 shows the configuration register. it contains three fields. the first is the width field. this field allows the num- ber of dq/dqn pins used for memory read and write accesses to be adjusted . the sle field enables data to be writ- ten into the memory through the serial interface using the wdsl register. figure 19 shows the power management register. it contains two fields. the first is the px field. when this field is written with a 1, the memory component transitions from powerdown to active state. it is usually unnecessary to write a 0 into this field; this is done automatically by the pdn command in a colx packet. the pst field indicates the current power state of the memory component. figure 20 shows the write data serial load register. it permits data to be written into memo ry via the serial interface. figure 23 shows the refresh bank control register. it contains two fields: bank and mbr. the bank field is read-write and contains the bank address us ed by self-refresh during the powerdown state. the mbr field controls how many banks are refreshed during each refresh operation. figure 24, figure 25, and figure 26 show different fields of the refresh row regis- ter (high, middle, and low). this read-write field contains the row address used by self- and auto-refresh. see ?refresh trans- actions? on page 40 for more details. figure 28 and figure 29 show the current calibration 0 and 1 registers. they contain the ccvalue0 and ccvalue1 fields, respectively. these are read-write fields which control the amount of iol current driven by the dq and dqn pins during a read transaction. th e current calibration 0 register controls the even-numbered dq and dqn pins, and the cur- rent calibration 1 controls the odd-numbered dq and dqn pins. figure 32 shows the test registers. it is used during device test- ing. it is not to be read or written during normal operation. figure 33 shows the dly register. this is used to set the value of t cac and t cwd used by the component. see ?timing parameters? on page 62 figure 17 serial identification (sid) register 7 6 5 4 3 2 1 0 read-only register sid[7:0] resets to 00000000 2 sid[5:0] reserved sid[5:0] - serial identification field. this field contains the serial identification value for the device. the value is compared to the sid[5:0] field of a serial transaction to determine if the serial transaction is directed to this device. the serial identification value is set during the initialization sequence. serial identification register sadr[7:0]: 00000001 2
preliminary data sheet e0643e30 (ver. 3.0) 35 edx5116abse figure 18 configuration (cfg) register figure 19 power management (pm) register figure 20 write data serial load (wdsl) control register 7 6 5 4 3 2 1 0 read/write register cfg[7:0] resets to 00000100 2 width[2:0] rsrv width[2:0] - device interface width field. 000 2 - reserved. 001 2 - reserved 010 2 - x4 device width 011 2 - x8 device width 100 2 - x16 device width 101 2 , 110 2 , 111 2 - reserved sle - serial load enable field. 0 2 - wdsl-path-to-memory disabled 1 2 - wdsl-path-to-memory enabled configuration register sadr[7:0]: 00000010 2 rsrv sle rsrv 7 6 5 4 3 2 1 0 read/write register pm[7:0] resets to 00000000 2 px reserved px - powerdown exit field. (write-one-only, read=zero) 0 2 - powerdown entry - do not write zero - use pdn command 1 2 - powerdown exit - write one to exit pst[1:0] pst[1:0] - power state field (read-only). 00 2 - powerdown (with self-refresh) 01 2 - active/active-idle 10 2 - reserved 11 2 - reserved power management register sadr[7:0]: 00000011 2 7 6 5 4 3 2 1 0 read/write register wdsl[7:0] resets to 00000000 2 wdsd[7:0] - writing to this register places eight bits of data into the serial-to-parallel conversion logic (the ?demux? block of figure 2). writing to this register ?2x16? times accumulates a full ?t cc ? worth of write data. a subsequent wr command (with sle=1 in cfg register in figure 32) will write this data (rather than dq data) to the sense amps of a memory bank. the shifting order of the write data is shown in table 10. write data serial load control register sadr[7:0]: 00000100 2 wdsd[7:0]
preliminary data sheet e0643e30 (ver. 3.0) 36 edx5116abse figure 21 rq scan high (rqh) register figure 22 rq scan low (rql) register figure 23 refresh bank (refb) control register 7 6 5 4 3 2 1 0 read/write register rqh[7:0] resets to 00000000 2 rqh[3:0] - latched value of rq[11:8] in rq wire test mode. rq scan high register sadr[7:0]: 00000110 2 rqh[3:0] reserved 7 6 5 4 3 2 1 0 read/write register rql[7:0] resets to 00000000 2 rql[7:0] - latched value of rq[7:0] in rq wire test mode. rq scan low register sadr[7:0]: 00000111 2 rql[7:0] 7 6 5 4 3 2 1 0 read/write register refb[7:0] resets to 00000000 2 reserved bank[2:0] - refresh bank field. this field returns the bank address for the next self-refresh oper- ation when in powerdown power state. mbr[1:0] - multi-bank and multi-row refresh control field. 00 2 - single-bank refresh. 10 2 - reserved 01 2 - reserved 11 2 - reserved refresh bank control register sadr[7:0]: 00001000 2 bank[2:0] mbr[1:0]
preliminary data sheet e0643e30 (ver. 3.0) 37 edx5116abse figure 24 refresh high (refh) row register figure 25 refresh middle (refm) row register figure 26 refresh low (refl) row register figure 27 io configuration (iocfg) register 7 6 5 4 3 2 1 0 read/write register refh[7:0] resets to 00000000 2 r[18:16] reserved reserved - refresh row field. this field contains the high-order bits of the row address that will be refreshed during the next re fresh interval. this row address will be incremented after a refi command for auto-refresh, or when the bank[2:0] field for the refb register equals the max- imum bank address for self-refresh. refresh high row register sadr[7:0]: 00001001 2 7 6 5 4 3 2 1 0 read/write register refm[7:0] resets to 00000000 2 r[11:8] - refresh row field. this field contains the middle-ord er bits of the row address that will be refreshed during the next refresh interval. this row address will be incremented after a refi command for auto- refresh, or when the bank[2:0 ] field for the refb register equals the maximum bank address for self-refresh. refresh middle row register sadr[7:0]: 00001010 2 r[11:8] reserved 7 6 5 4 3 2 1 0 read/write register refl[7:0] resets to 00000000 2 r[7:0] r[7:0] - refresh row field. this field contains the low-order bi ts of the row address that will be refreshed during the next re fresh interval. this row address will be incremented after a refi command for auto-refresh, or when the bank[2:0] field for the refb register equals the max- imum bank address for self-refresh. refresh low row register sadr[7:0]: 00001011 2 7 6 5 4 3 2 1 0 read/write register iocfg[7:0] resets to 00000000 2 odf[1:0] odf[1:0] - overdrive function field. 00 - nominal v osw,dq range 01 - reserved 10 - reserved 11 - reserved io configuration register sadr[7:0]: 00001111 2 reserved
preliminary data sheet e0643e30 (ver. 3.0) 38 edx5116abse figure 28 current calibration 0 (cc0) register figure 29 current calibration 1 (cc1) register figure 30 read only memory 0 (rom0) register figure 31 read only memory 1 (rom1) register 7 6 5 4 3 2 1 0 read/write register cc0[7:0] resets to 00001111 2 ccvalue0[5:0] reserved ccvalue0[5:0] - current calibration value field. this field controls the amount of current drive for the even-num- bered dq and dqn pins. current calibration 0 register sadr[7:0]: 00010000 2 7 6 5 4 3 2 1 0 read/write register cc1[7:0] resets to 00001111 2 ccvalue1[5:0] reserved ccvalue1[5:0] - current calibration value field. this field controls the amount of current drive for the odd-num- bered dq and dqn pins. current calibration 1 register sadr[7:0]: 00010001 2 7 6 5 4 3 2 1 0 read-only register rom0[7:0] resets to 0010mmmm mask[3:0] - version number of mask (0001 2 is first version). vendor[3:0] - vendor number for component: 0010 - elpida read only memory 0 register sadr[7:0]: 00010110 2 mask[3:0] reserved vendor[3:0] 7 6 5 4 3 2 1 0 read-only register rom0[7:0] resets to bbrrrccc cb[2:0] - column address bits: #bits = 6 +cb[2:0] rb[2:0] - row address bits: #bits = 10 +rb[2:0] bb[1:0] - bank address bits: #bits = 2 +bb[1:0] these three fields indicate how many column, row, and bank address bits are present. an offset of {6,10,2} is added to the field value to give the number of address bits. read only memory 1 register sadr[7:0]: 00010111 2 cb[2:0] rb[2:0] bb[1:0]
preliminary data sheet e0643e30 (ver. 3.0) 39 edx5116abse figure 32 test register figure 33 delay (dly) control register 7 6 5 4 3 2 1 0 read/write register test[7:0] resets to 00000000 2 wte - wire test enable wtl - wire test latch test register sadr[7:0]: 00011000 2 reserved wte wtl 7 6 5 4 3 2 1 0 read/write register dly[7:0] resets to 00110110 2 cac[3:0] - programmed value of t cac timing parameter: 0110 2 - t cac = 6*t cycle 1000 2 - t cac = 8*t cycle 0111 2 - t cac = 7*t cycle others - reserved. cwd[3:0] dly register sadr[7:0]: 00011111 2 cac[3:0] cwd[3:0] - programmed value of t cwd timing parameter: 0011 2 - t cwd = 3*t cycle 0100 2 - t cwd = 4*t cycle others - reserved. following sadr [7:0] registers are reserved: 00010010 2 , 00010011 2 , 00010100 2 , 00010101 2 , 00011001 2 , 00011010 2 , 00011011 2 , 00011100 2 , 00011101 2 , 10000000 2 - 10001111 2 .
preliminary data sheet e0643e30 (ver. 3.0) 40 edx5116abse maintenance operations refresh transactions figure 34 contains two timing di agrams showing examples of refresh transactions. the top timing diagram shows a single refresh operation. bank ba is a ssumed to be closed (in a pre- charged state) when a refa command is received in a rowp packet on clock edge t 0 . the refa command causes the row addressed by the refr regist er (refh/refm/refl) to be opened (sensed) and placed in the sense amp array for the bank. note that the refa and refi commands are similar to the act command functionally; both specify a bank address and delay value, and both cause the selected bank to open (to become sensed.) the difference is that the act command is accompanied by a row address in the rowa packet, while the refa and refi commands use a row address in the refr register (refh/refm/refl). after a time t ras , a rowp packet with refp command to bank ba is presented. this caus es the bank to be closed (pre- charged), leaving the bank in the same state as when the refresh transaction began. note that the refp command is equivalent to the pre com- mand functionally; both specify a bank address and delay value, and both cause the selected ba nk to close (to become pre- charged). after a time t rp , another rowp packet with refa command to bank bb is presented (banks ba and bb are the same in this example). this starts a second refresh cycle. each refresh transaction requires a total time t rc = t ras + t rp , but refresh transactions to different banks may be interleaved like normal read and write transactions. each row of each bank must be refreshed once in every t ref interval. this is shown with the fourth rowp packet with a refa command in the top timing diagram. interleaved refresh transactions the lower timing diagram in figure 34 represents one way a memory controller might handle refresh maintenance in a real system. a series of eight rowp packets with refa commands (except for the last which is a refi command) are presented starting at edge t 0 . the packets are spaced with intervals of t rr . each refa or refi command is addressed to a different bank (ba through bh) but uses the same row address from the refr (refh/refm/refl) register. the eighth refi com- mand uses this address and then increments it so the next set of eight refa/refi commands will refresh the next set of rows in each bank. a series of eight rowp packets with refp commands are presented effectively at edge t 10 (a time t ras after the first rowp packet with a refa command). the packets are spaced with intervals of t pp . like the refa/refi commands, each refp command is addressed to a different bank (ba through bh). this burst of eight refresh transactions fully utilizes the mem- ory component. however, other read and write transactions may be interleaved with the re fresh transactions before and after the burst to prevent any loss of bus efficiency. in other words, a rowa packet with act command for a read or write could have been presented at edge t -4 (a time t rr before the first refresh transaction starts at edge t 0 ). also, a rowa packet with act command for a read or write could have been presented at edge t 36 (a time t rr after the last refresh transac- tion starts at edge t 32 ). in both cases, the other request packets for the interleaved read or write accesses (the precharge com- mands and the read or write commands) could be slotted in among the request packets for the refresh transactions.
preliminary data sheet e0643e30 (ver. 3.0) 41 edx5116abse figure 34 refresh transactions t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 transaction a: ref a0 = {ba,refr} a1 = {ba} t cycle t 24 t 25 t 26 t 27 t 28 t 29 t 30 t 31 t 33 t 34 t 35 t 36 t 37 t 38 t 39 t 40 t 41 t 42 t 43 t 44 t 45 t 46 t 47 t 32 refresh transaction interleaved refresh example b0 refa t rr a1 refp a0 refa transaction b: ref a0 = {ba,refr} b1 = {bb} bb = ba t rc c0 refa d0 refa e0 refa t cycle a1 refp b1 refp c1 refp d1 refp f0 refa g0 refa h0 refi e1 refp f1 refp g1 refp h1 refp g0 refa h0 refa a0 refa b0 refa c0 refa d0 refa e0 refa f0 refa a0 refa b0 refa t ref t rp t ras c0 refa transaction c: ref c0 = {bc,refr} c1 = {bc} bc/rc = ba/ra transaction a: ref a0 = {ba,refr} a1 = {ba} transaction b: ref b0 = {bb,refr} b1 = {bb} transaction c: ref c0 = {bc,refr} c1 = {bc} transaction d: ref d0 = {bd,refr} d1 = {bd} transaction e: ref e0 = {be,refr} e1 = {be} ba,bb,bc,bd, transaction f: ref f0 = {bc,refr} f1 = {bf} transaction g: ref g0 = {bd,refr} g1 = {bg} transaction h: ref h0 = {be,refr} h1 = {bh} different banks. bh are be,bf,bg and i0 refa transaction i: ref i0 = {ba,refr+1} i1 = {bi} bi = ba this refi increments refr dq15..0 dqn15..0 cfm cfmn rq11..0 (act) rq11..0 (pre) rq11..0 (all) dq15..0 dqn15..0 cfm cfmn rq11..0 (act) rq11..0 (pre) rq11..0 (all) dq15..0 dqn15..0 cfm cfmn rq11..0 e1 refp f1 refp g1 refp h1 refp a1 refp b1 refp c1 refp d1 refp i0 refa
preliminary data sheet e0643e30 (ver. 3.0) 42 edx5116abse calibration transactions figure 35 shows the calibration transaction diagrams for the xdr dram device. there is one calibration operation sup- ported: calibration of the output current level i ol for each dqi and dqni pin. the output current calibration sequence is shown in the upper diagram. it begins when a period of t cmd-calc is observed after the last rq packet (wit h command ?cmd a? in this example). no request pa ckets should be issued in this period. a colx packet with a?calc b? command is then issued to start the current calibration sequence. a period of t calce is observed after this packet. no request packets should be issued during this period. a colx packet with a ?cale c? command is then issued to end the current calibration sequence. a period of t cale-cmd is observed after this packet. no request packets should be issued during this period. the first requ est packet may then be issued (with command ?cmd d? in this example). a second current cali bration sequence must be started within an interval of t calc . in this example, the next colx packet with a ?calc e? command starts a subsequent sequence. the dynamic termination calibration sequence is shown in the lower diagram. note that this memory component does not use this sequence; termination calibration is performed during the manufacturing process. however, the termination sequence shown will be issued by the controller for those memory com- ponents which do use a period ic calibration mechanism. it begins when a period of t cmd-calz is observed after the packet at edge t 0 (with command cmda in this example). no request packets should be issued in this period. a colx packet with a calz command is then issued at edge t 3 to start the termination calibration sequence. a second period of t calze is observed after this packet. no request packets should be issued during this period. a colx packet with a cale command is then issued at edge t 6 to end the termination calibration sequence. a third period of t cale-cmd is observed after this packet. no request packets should be issued during this period. the first request packet may be issued at edge t 12 (with command cmdd in this exam- ple). a second termination calibrat ion sequence must be started within an interval of t calz . in this example, the next colx packet with a calz command occurs at edge t 20 . note that the labels for the cfm clock edges (of the form t i ) are not to scale, and are used to identify events in the diagrams.
preliminary data sheet e0643e30 (ver. 3.0) 43 edx5116abse figure 35 calibration transactions t 0 t 1 t 2 t 3 cfm rq11..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn packet a: any cmd t cycle current calibration transaction packet b: calc t calc termination calibration transaction a t cale-cmd, packet d: any cmd c cale e calc a cmd d cmd t 0 t 1 t 2 t 3 cfm rq11..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn t cycle t calz t cale-cmd, c cale e calz a cmd d cmd dq15..0 dqn15..0 dq15..0 dqn15..0 rq11..0 cfm cfmn cfm cfmn rq11..0 t calce, packet e: calc packet c: cale t cmd-calc b calc t cmd-calz b calz packet a: any cmd packet b: calz packet d: any cmd packet e: calz packet c: cale t calze, a) edx5116abse does not use terminat ion calibration transaction sequence.
preliminary data sheet e0643e30 (ver. 3.0) 44 edx5116abse power state management figure 36 shows power state transition diagrams for the xdr dram device. there are two power states in the xdr dram: powerdown and active. powerdown state is to be used in applications in which it is necessary to shut down the cfm/ cfmn clock signals. in this state, the contents of the storage cells of the xdr dram will be retained by an internal state machine which performs periodic refresh operations using the refb and refr control registers. the upper diagram shows the sequence needed for power- down entry. prior to starting the sequence, all banks of the xdr dram must be precharged so they are left in a closed state. also, all 2 3 banks must be refres hed using the current value of the refr registers, and the refr registers must not be incremented with the refi command at the end of this special set of refresh transactions . this ensures that no matter what value has been left in the refb regist er, no row of any bank will be skipped when automatic refresh is first started in powerdown. there may be some banks at the current row value in the refr registers that are refreshed twice during the powerdown entry process. after the last request packet (with the command cmda in the upper diagram of the figure), an interval of t cmd-pdn is observed. no request packets s hould be issued during this period. a colx packet with the pdn co mmand is issued after this interval, causing the xdr dram to enter powerdown state after an interval of t pdn-entry has elapsed (this is the parame- ter that should be used for ca lculating the power dissipation of the xdr dram). the cfm/cfmn clock signals may be removed a time t pdn-cfm after the colx packet with the pdn command. also, the termination voltage supply may be removed (set to the ground reference) from the vterm pins a time t pdn-cfm after the colx packet with the pdn com- mand. the voltage on the dq/dqn pins will follow the volt- age on the vterm pins during powerdown entry. when the xdr dram is in powerdown, an internal fre- quency source and state machin e will automatically generate internal refresh transactions . it will cycle through all 2 3 state combinations of the refb register. when the largest value is reached and the refb value wraps around, the refr register is incremented to the next value. the refb and refr values select which bank and which row are refreshed during the next automatic refres h transaction. the lower diagram shows the sequence needed for powerdown exit. the sequence is started with a serial broadcast write (sbw command) transaction using the serial bus of the xdr dram. this transaction writes the value ?00000001? to the power management (pm) regi ster (sadr=?00000011?) of all xdr drams connected to the serial bus. this sets the px bit of the pm register, causing the xdr drams to return to active power state. the cfm/cfmn clock signals must be stable a time t cfm- pdn before the end of the sbw tr ansaction. also, the termina- tion voltage supply must be rest ored to its normal operating point (v term,drsl ) on the vterm pins a time t cfm-pdn before the end of the sbw tr ansaction. the voltage on the dq/dqn pins will follow the voltage on the vterm pins during powerdown exit. the xdr dram will enter active state after an interval of t pdn-exit has elapsed from the end of the sbw transaction (this is the parameter that should be used for calculating the power dissipation of the xdr dram). the first request packet may be issued after an interval of t pdn-cmd has elapsed from the end of the sbw transaction, and must contain a ?refa? command in a rowp packet . in this example, this packet is denoted with the command ?refa 1?. no other request packets should be issued during this t pdn- cmd interval. all ?n? banks (in the example, n=2 3 ) must be refreshed using the current value of the refr registers. the ?nth? refresh transaction will use a ?refi? command to increment the refr register (instead of a ?refr? command). this ensures that no matter what value has be en left in the refb register, no row of any bank will be skipped when normal refresh is restarted in active state. ther e may be some banks at the cur- rent row value in the refr registers that are refreshed twice during the powerdown exit process. note that during the powerdown state an internal time source keeps the device refreshed. however, during the t pdn-cmd interval, no internal refresh op erations are performed. as a result, an additional burst of refresh transact ions must be issued after the burst of ?n? transactions described above. this second burst consists of ?m? refresh transactions: m = ceiling[2 3 *2 12 *t pdn-cmd /t ref ] where ?2 12 ? is the number of rows per bank, and ?2 3 ? is the number of banks. every ?nth ? refresh transa ction (where n=2 3 ) will use a ?refi? command (to increment the refr register) instead of a ?refa? command.
preliminary data sheet e0643e30 (ver. 3.0) 45 edx5116abse figure 36 power state management transaction a: last precharge command t cycle powerdown entry cmd transaction b: pdn t cmd-pdn transaction 1: refa t cycle powerdown exit transaction 2: refa s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 18 s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 16 ?0? ?0? scmd power-up transaction t cyc,sck a pdn t pdn-entry powerdown state... t cycle 1 refa n refp ?1? ?1? ?0? ?0? start t pdn-exit t pdn-cmd 2 refa transaction n: refi n-1 refp t pdn-cfm no signal no signal t cfm-pdn ....powerdown state rst sck cmd dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 dq15..0 dqn15..0 cfm cfmn rq11..0 a pdn b 2 4 3 5 0 1 ?0? ?0? 2?h0,sid[5:0] 2 4 3 5 0 1 6 7 swd[7:0] ?0? ?0? sdi (input) sdo (output) 2 4 3 5 0 1 6 7 sadr[7:0] n-2 refp n refi the final refa/refi command in crements the refr register transaction n-1: refa t pdn-cmd
preliminary data sheet e0643e30 (ver. 3.0) 46 edx5116abse initialization figure 37 shows the topology of the serial interface signals of a xdr dram system. the three signals rst, cmd, and sck are transmitted by the controller and are received by each xdr dram device along the bus. the signals are terminated to the vterm supply through termination components at the end farthest from the controller. the sdi input of the xdr dram device furthest from the controller is also terminated to vterm. the sdo output of each xdr dram device is transmitted to the sdi input of the next xdr dram device (in the direction of the contro ller). this sdo/sdi daisy-chain topology continues to the controller, where it ends at the srd input of the controller. all the serial interface signals are low- true. all the signals use rsl signaling circuits, except for the sdo output which uses cmos signaling circuits. figure 37 serial interface system topology figure 38 shows the initialization ti ming of the serial interface for the xdr dram[k] device in the system shown above. prior to initialization, the rst is held at zero. the cmd input is not used here, and should also be held at zero. note that the inputs are all sampled by the negative edge of the sck clock input. the sdi input for the xdr dram[0] device is zero, and is unknown for the remaining devices. on negative sck edge s 8 the rst input is sampled one. it is sampled one on the next four edges, and is sampled zero on edge s 12 a time t rst-10 after it was first sampled one. the state of the control registers in the xdr dram device are set to their reset values after the first edge (s 8 ) in which rst is sam- pled one. figure 38 initialization timing for xdr dram[k] device the sdi inputs will be samp led one within a time t rst-sdo,11 after rst is first sampled one in all the xdr drams except for xdr dram[0]. xdr dram[0]?s sdi input will always be sampled zero. xdr dram[k] will see its rst input sampled zero at s 12 , and will then see its sdi input sampled zero at s 16 (after sdi had xdr dram rst cmd sck sdo sdi xdr dram rst cmd sck sdo sdi xdr dram rst cmd sck sdo sdi controller rst cmd sck srd ... ... vterm s 0 s 2 s 4 s 6 s 8 s 10 s 12 s 14 s 18 s 20 s 22 s 24 s 26 s 28 s 30 s 32 s 34 s 36 s 38 s poweron s 16 t cyc,sck rst sdi (input) sck cmd sdo (output) ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?1? ?1? ?1? ?1? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?x? ?x? ?x? ?x? ?1? ?1? ?x? ?1? ?1? ?1? ?1? ?1? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?x? ?x? ?x? ?x? ?1? ?1? ?x? ?1? ?1? ?1? ?1? ?1? ?0? ?0? ?1? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? ?0? t rst-sdi,00 t rst-sdo,11 t sdi-sdo,00 t rst-10 = k * t cyc,sck t coreinit 0 1 0 1 0 1 0 1 0 1 t rst-sck
preliminary data sheet e0643e30 (ver. 3.0) 47 edx5116abse previously been sampled one). this interval (measured in t cyc,sck units) will be equal to the index [k] of the xdr dram device along the serial interface bus. in this example, k is equal to 4. this is because each xdr dram device will drive its sdo output zero around the sck edge a time t sdi-sdo,00 after its sdi input is sampled zero. in other words, the xdr dram[0] device will see rst and sdi both sampled zero on the same edge s 12 (t rst-sdi,00 will be 0*t cyc,sck units), and will drive its sdo to zero around the subsequent edge (s 13 ). the xdr dram[1] device will see sdi sampled zero on edge s 13 (t rst-sdi,00 will be 1*t cyc,sck units), and will drive its sdo to zero around the subsequent edge (s 14 ). the xdr dram[2] device will see sdi sampled zero on edge s 14 (t rst-sdi,00 will be 2*t cyc,sck units), and will drive its sdo to zero around the subsequent edge (s 15 ). this continues until the last xdr dram device drives the srd input of the controller. each xdr dram device con- tains a state machine which measures the interval t rst-sdi,00 between the edges in which rst and sdi are both sampled zero, and uses this value to set the sid[5:0] field of the sid (serial identification) register. th is value allows directed read and write transactions to be made to the individual xdr dram devices. table 9 summarizes the range of the timing parameters used for initializati on by the serial interface bus. xdr dram initialization overview [1] apply voltage tovdd, vterm, and vref pins. vterm and vref voltages must be less or equal to vdd voltage at all times. wait a time interval t coreinit . [2] assert rst, sck, sdi, and cmd to logical zero. then: - pulse sck to logical one, then to logical zero four times. - assert rst to logical one. reset circuit places xdr dram into low-power state (i dentical to power-on reset). - perform remaining initiali zation sequence in figure 38. [3] xdr dram has valid serial id and all registers have default values that are define d in figure 17 through figure 33. [4] perform broadcast or directed register writes to adjust regis- ters which need a value differe nt from their default value. [5] perform powerdown exit sequence shown in figure 36. this includes the activity from sck cycle s 0 through the final refp command. [6] perform termination/curr ent calibration. the calz/ cale sequence shown in figure 35 is issued 128 times, then the calc/cale sequence is issu ed 128 times. after this, each sequence is issued once every t calz or t calc interval. [7] condition the xdr dram banks by performing a refa/ refi activate and refp precharge operation to each bank eight times. this can be interleaved to save time. the row address for the activate operation will step through eight suc- cessive values of the refr registers. the sequence between cycles t 0 and t 32 in the interleaved refresh example in figure 34 could be performed eigh t times to satisfy this condi- tioning requirement. table 9 initialization timing parameters symbol parameter minimum maximum units figure(s) t rst,10 number of cycles between rst being sampled one and rst being sampled zero. 2 - t cyc,sck - t rst-sdo,11 number of cycles between rst being sampled one and sdo being driven to one. 1 1 t cyc,sck - t rst-sdi,00 number of cycles between rst bein g sampled zero (after being sam- pled one for t rst,10,min or more cycles) and sdi being sampled zero. this will be equal to the index [k] of the xdr dram device along the serial interface bus. 0 63 t cyc,sck - t sdi-sdo,00 number of cycles between sdi be ing sampled one (after rst has been sampled one for t rst,10,min or more cycles and is then sampled zero) and sdo being driven to one. 1 1 t cyc,sck - t rst-sck the number of sck falling edges after the first sck falling edge in which rst is sampled one. 20 - t cyc,sck -
preliminary data sheet e0643e30 (ver. 3.0) 48 edx5116abse xdr dram pattern load with wdsl reg the xdr memory system requires a method of deterministi- cally loading pattern data to xdr drams before beginning receive timing calibration (rx tcal). the method employed by the xdr drams to achieve this is called write data serial load (wdsl). a wdsl packet sends one-byte of serial data which is serially shifted into a holding register within the xdr dram. initialization software sends a sequence of wdsl packets, each of which shifts the new byte in and advances the shifter by 8 positions. in this way, xdr drams of varying widths can be loaded with a single command type. each sequence of wdsl packet s will load one full column of data to the internal holding regi ster of the target xdr dram. depending upon the ratio of na tive device width to pro- grammed width, there may be mo re than one sub-column per column. after loading a full column, a series of wr com- mands will be issued to sequentially transfer each sub-column of the column to the xdr dram core(s), based upon the sc[3:0] bits. . table 10 xdr dram wdsl-to-core/dq/sc map (first generation x16/x8/x4 xdr dram , bl=16) dq pins used core word wdsl core word load order x16 x8 x4 x4 x8 x16 wd[n][15:0] sc[3:2] =xx sc[3:2] = 0x sc[3:2] = 1x sc[3:2] = 00 sc[3:2] = 01 sc[3:2] = 10 sc[3:2] = 11 logical view of xdr dram word written (1 = written, 0 = not written) dq0 dq0 dq0 wd[0][15:0] wdsl word 8 1 1 01 0 0 0 dq1 dq1 dq1 wd[1][15:0] wdsl word 7 1 1 01 0 0 0 dq2 dq2 dq2 wd[2][15:0] wdsl word 12 1 1 01 0 0 0 dq3 dq3 dq3 wd[3][15:0] wdsl word 3 1 1 01 0 0 0 dq0 dq4 dq4 wd[4][15:0] wdsl word 10 1 1 0 01 0 0 dq1 dq5 dq5 wd[5][15:0] wdsl word 5 1 1 0 01 0 0 dq2 dq6 dq6 wd[6][15:0] wdsl word 14 1 1 0 01 0 0 dq3 dq7 dq7 wd[7][15:0] wdsl word 1 1 1 0 01 0 0 dq0 dq0 dq8 wd[8][15:0] wdsl word 9 1 01 0 01 0 dq1 dq1 dq9 wd[9][15:0] wdsl word 6 1 01 0 01 0 dq2 dq2 dq10 wd[10][15:0] wdsl word 13 1 01 0 01 0 dq3 dq3 dq11 wd[11][15:0] wdsl word 2 1 01 0 01 0 dq0 dq4 dq12 wd[12][15:0] wdsl word 11 1 01 0 0 01 dq1 dq5 dq13 wd[13][15:0] wdsl word 4 1 01 0 0 01 dq2 dq6 dq14 wd[14][15:0] wdsl word 15 1 01 0 0 01 dq3 dq7 dq15 wd[15][15:0] wdsl word 0 1 01 0 0 01 physical view of xdr dram word written (1 = written, 0 = not written) dq2 dq6 dq14 wd[14][15:0] wdsl word 15 1 01 0 0 01 dq6 wd[6][15:0] wdsl word 14 1 1 0 01 0 0 dq2 dq10 wd[10][15:0] wdsl word 13 1 01 0 01 0 dq2 wd[2][15:0] wdsl word 12 1 1 01 0 0 0 dq0 dq4 dq12 wd[12][15:0] wdsl word 11 1 01 0 0 01 dq4 wd[4][15:0] wdsl word 10 1 1 0 01 0 0 dq0 dq8 wd[8][15:0] wdsl word 9 1 01 0 01 0 dq0 wd[0][15:0] wdsl word 8 1 1 01 0 0 0
preliminary data sheet e0643e30 (ver. 3.0) 49 edx5116abse . dq1 dq1 dq1 wd[1][15:0] wdsl word 7 1 1 01 0 0 0 dq9 wd[9][15:0] wdsl word 6 1 01 0 01 0 dq5 dq5 wd[5][15:0] wdsl word 5 1 1 0 01 0 0 dq13 wd[13][15:0] wdsl word 4 1 01 0 0 01 dq3 dq3 dq3 wd[3][15:0] wdsl word 3 1 1 01 0 0 0 dq11 wd[11][15:0] wdsl word 2 1 01 0 01 0 dq7 dq7 wd[7][15:0] wdsl word 1 1 1 0 01 0 0 dq15 wd[15][15:0] wdsl word 0 1 01 0 0 01 table 10 xdr dram wdsl-to-core/dq/sc map (first generation x16/x8/x4 xdr dram , bl=16) dq pins used core word wdsl core word load order x16 x8 x4 x4 x8 x16 wd[n][15:0] sc[3:2] =xx sc[3:2] = 0x sc[3:2] = 1x sc[3:2] = 00 sc[3:2] = 01 sc[3:2] = 10 sc[3:2] = 11 ta b l e 11 core data word-to-wdsl format a dq serialization order cfm/pclk cycle cycle 0 cycle 1 symbol (bit) time t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 bit transmitted on dq pins d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 wdsl byte/bit transfer order core word core word wd[n][15:0] wdsl byte order wdsl byte 0 wdsl byte 1 swd field of serial packet 7654321076543210 bit transmitted on cmd pind15d11d7 d3d14d10d6 d2d13d9 d5 d1d12d8 d4 d0 a. applies for firs t generation x16/x8/x4 xdr dram with bl=16.
preliminary data sheet e0643e30 (ver. 3.0) 50 edx5116abse special feature description dynamic width control this xdr dram device includes a feature called dynamic width control. this permits the de vice to be configured so that read and write data can be access ed through differing widths of dq pins. figure 39 shows a diagram of the logic in the path of the read data (q) and write data (d) that accomplishes this. the read path is on the right of the figure. there are 16 sets of s signals (the internal data bus connecting to the sense amps of the memory core), with 16 signals in each set. when the xdr dram device is configured for maximum width operation (using the width[2:0] field in the cfg register), each set of 16 s signals goes to one of the 16 dq pins (via the q[15:0][15:0] read bus) and are driven out in the 16 time slots for a read data packet. when the xdr dram device is configured for a width that is less than the maximum, some of the dq pins are used and the rest are not used. the sc[3:0] field of the col request packets select which s[15:0][15: 0] signals are passed to the q[15:0][15:0] read bus an d driven as read data. figure 40 shows the mapping from the s bus to the q bus as a function of the width[2:0] regist er field and the sc[3:0] field of the col request packet. there is a separate table for each valid value of width[2:0]. in each table, there is an entry in the left column for each valid value of sc[3:0]. this field should be treated as an extensio n of the c[9:4] column address field. the right hand column sh ows which set of s[15:0][15:0] signals are mapped to the q read data bus for a particular value of sc[3:0]. for example, assume that the wi dth[2:0] value is ?010?, indi- cating a device width of x4. look ing at the appropriate table in figure 40, it may be seen that in the sc[3:0] field, the sc[1:0] sub-column address bits are not used. the remaining sc[3:0] address bit(s) se lects one of the 64-bit blocks of s bus signals, causing them to be driven onto th e q[3:0][15:0] read data bus, which in turn is driven to the dq3..0/dqn3..0 data pins. the q[15:4][15:0] signals and dq15..4/dqn15..4 data pins are not used for a device width of x4. the write path is shown on the left side of figure 39. as before, there are 16 sets of s si gnals (the internal data bus con- necting to the sense amps of the memory core), with 16 signals in each set. when the xdr dram device is configured for maximum width operation (using the width[2:0] field in the cfg register), each set of 16 s signals is driven from one of the 16 dq pins (via the d[15:0][15:0] write bus) from each of the 16 time slots for a write data packet. figure 40 also shows the mapping from the d bus to the s bus as a function of the width[2:0] register field and the sc[3:0] field of the col request packet. there is a separate table for each valid value of width[2:0]. in each table, there is an entry in the left column for each vali d value of sc[3:0]. this field should be treated as an extensi on of the c[9:4] column address field. the right hand column shows which set of s[15:0][15:0] signals are mapped from the d read data bus for a particular value of sc[3:0]. figure 39 multiplexers for dynamic width control dynamic width demux (wr) 16x16 16x16 dynamic width mux (rd) 16x16 s[15:0][15:0] 16x16 d[15:0][15:0] width[2:0] sc[3:0] width[2:0] sc[3:0] 4+3 4+3 q[15:0][15:0] byte mask (wr) d1[15:0][15:0] 16x16 m[7:0] 8
preliminary data sheet e0643e30 (ver. 3.0) 51 edx5116abse the block diagram in figure 39 indicates that the dynamic width logic is positioned after the serial-to-parallel conversion (demux block) in the data recei ver block and before the paral- lel-to-serial conversion (mux block) in the data transmitter block (see also the block diagram in figure 2). the block dia- gram is shown in this manner so the functionality of the logic can be made as clear as possi ble. some implementations may place this logic in the data rece iver and transmitter blocks, per- forming the mapping in figure 40 on the serial data rather than the parallel data. however, this design choice will not affect the functionality of the dynamic width lo gic; it is strictly an imple- mentation decision. figure 40 d-to-s and s-to-q mapping fo r dynamic width control a8 width[2:0]=000 (x1 device width) 000 s[0][15:0] 001 s[1][15:0] 010 s[2][15:0] 011 s[3][15:0] 100 s[4][15:0] 101 s[5][15:0] 110 s[6][15:0] 111 s[7][15:0] sc[2:0] d[0][15:0] q[0][15:0] width[2:0]=001 (x2 device width) 00x s[4,0][15:0] 01x s[5,1][15:0] 10x s[6,2][15:0] 11x s[7,3][15:0] sc[2:0] d[1:0][15:0] q[1:0][15:0] width[2:0]=010 (x4 device width) 0xx s[6,2,4,0][15:0] 1xx s[7,3,5,1][15:0] sc[2:0] d[3:0][15:0] q[3:0][15:0] width[2:0]=011 (x8 device width) xxx s[7:0][15:0] sc[2:0] d[7:0][15:0] q[7:0][15:0] width[2:0]=000 (x1 device width) 0000 s[0][15:0] 0001 s[1][15:0] 0010 s[2][15:0] 0011 s[3][15:0] 0100 s[4][15:0] 0101 s[5][15:0] 0110 s[6][15:0] 0111 s[7][15:0] 1000 s[8][15:0] 1001 s[9][15:0] 1010 s[10][15:0] 1011 s[11][15:0] 1100 s[12][15:0] 1101 s[13][15:0] 1110 s[14][15:0] 1111 s[15][15:0] sc[3:0] d[0][15:0] q[0][15:0] a16 width[2:0]=001 (x2 device width) 000x s[1:0][15:0] 001x s[3:2][15:0] 010x s[5:4][15:0] 011x s[7:6][15:0] 100x s[9:8][15:0] 101x s[11:10][15:0] 110x s[13:12][15:0] 111x s[15:14][15:0] sc[3:0] d[1:0][15:0] q[1:0][15:0] width[2:0]=010 (x4 device width) 00xx s[3:0][15:0] 01xx s[7:4][15:0] 10xx s[11:8][15:0] 11xx s[15:12][15:0] sc[3:0] d[3:0][15:0] q[3:0][15:0] width[2:0]=011 (x8 device width) 0xxx s[7:0][15:0] 1xxx s[15:8][15:0] sc[3:0] d[7:0][15:0] q[7:0][15:0] width[2:0]=100 (x16 device width) xxxx s[15:0][15:0] sc[3:0] d[15:0][15:0] q[15:0][15:0] a a a) edx5116abse does not support 1 and 2 device width.
preliminary data sheet e0643e30 (ver. 3.0) 52 edx5116abse write masking figure 41 shows the logic used by the xdr dram device when a write-masked command (wrm) is specified in a colm packet. this masking logic permits individual bytes of a write data packet to be written or not written ac cording to the value of an eight bit write mask m[7:0]. in figure 41, there are 16 sets of 16 bit signals forming the d1[15:0][15:0] input bus for th e byte mask block. these are treated as 2x16 8-bit bytes: d1[15][15:8] d1[15][7:0] ... d1[1][15:8] d1[1][7:0] d1[0][15:8] d1[0][7:0] the eight bits of each byte is co mpared to the value in the byte mask field (m[7:0]). if they are not equal (ne), then the corre- sponding write enable signal (we) is asserted and the byte is written into the sense amplifier. if they are equal, then the cor- responding write enable signal (w e) is deasserted and the byte is not written into the sense amplifier. in the example of figure 41, a wrm command performs a masked write of a 64 byte data packet to all the memory devices connected to the rq bus (and receiving the com- mand). it is the job of the me mory controller to search the 64 bytes to find an eight bit data va lue that is not used and place it into the m[7:0] field. this will always be possible because there are 256 possible 8-bit values and there are only 64 possible val- ues used in the bytes in the data packet. figure 41 byte mask logic note that other systems might use a data transfer size that is different than the 64 bytes per t cc interval per rq bus that is used in the example in figure 41. figure 42 shows the timing of two successive wrm com- mands in colm packets. the timing is identical to that of two successive wr commands in col packets. the one difference byte mask (wr) s[0][7:0] 8 d1[0][7:0] 8 m[7:0] compare ne dynamic width demux (wr) 16x16 16x16 dynamic width mux (rd) 16x16 s[15:0][15:0] 16x16 d[15:0][15:0] width[2:0] sc[3:0] width[2:0] sc[3:0] 4+3 4+3 q[15:0][15:0] d1[15:0][15:0] 16x16 m[7:0] 8 1 8 8 d1[0][7:0] 8 s[0][15:8] 8 d1[0][15:8] 8 compare ne 1 8 8 d1[0][15:8] 8 8 8 compare ne 1 8 8 d1[15][7:0] 8 8 8 compare ne 1 8 8 d1[15][15:8] 8 s[15][15:8] we-msb [15] s[15][7:0] d1[15][15:8] d1[15][7:0] we-lsb [15] we-msb [0] we-lsb [0]
preliminary data sheet e0643e30 (ver. 3.0) 53 edx5116abse is that the colm packet includes a m[7:0] field that indicates the reserved bit pattern (for the eight bits of each byte) that indicates that the byte is not to be written. this requires that the alignment of bytes within the data packet be defined, and also that the bit numbering within each byte be defined (note that this was not necessary for the unmasked wr command). in the figure, bytes are contained within a single dq/dqn pin pair ? this is necessary so the dy namic width feature can be supported. thus, each pin pair carries two bytes of each data packet. byte[0] is transferred earlier than byte[1], and bit [0] of each byte (corresponding to m[0]) is transferred first, followed by the remaining bits in succession). figure 42 write-masked (wrm) transaction example t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cc t cwd t cycle a1 wrm a2 wrm d(a2) d(a1) dq15..0 dqn15..0 cfm cfmn rq11..0 [1] [0] [2] [4] [3] [5] [7] [6] [8] [10] [9] [11] [13] [12] [14] [15] [1] [0] [2] [4] [3] [5] [7] [6] [8] [10] [9] [11] [13] [12] [14] [15] dq0 dqn0 dq15 dqn15 ... ... t cac a1 rd q(a1) byte [0] bit- and byte-number- ing convention for write and read data packets. byte [15] byte [16+15] [1] [0] [2] [4] [3] [5] [7] [6] [8] [10] [9] [11] [13] [12] [14] [15] dq1 dqn1 byte [1] byte [16+0] byte [16+1]
preliminary data sheet e0643e30 (ver. 3.0) 54 edx5116abse multiple bank sets and the eraw feature figure 45 shows a block diagram of a xdr dram in which the banks are divided into two sets (called the even bank set and the odd bank set) according to the least-significant bit of the bank address field. this xdr dram supports a feature called ?early read after write? (hereafter called ?eraw?). the logic that accepts commands on the rq11..0 signals is capable of operating these two bank sets independently. in addition, each bank set connects to its own internal ?s? data bus (called s0 and s1). the receive interface is able to drive write data onto either of these internal data buses, and the transmit interface is able to sa mple read data from either of these internal data buses. thes e capabilities will permit the delay between a write column operation and a read column operation to be reduced, ther eby improving performance. figure 43 shows the timing previo usly presented in figure 12, but with the activity on the internal s data bus included. the write-to-read parameter t ? wr ensures that there is adequate turnaround time on the s bu s between d(a2) and q(c1). when eraw is supported with odd and even bank sets, the t ? wr,min parameter must be obeyed when the write and read column operations are to the sa me bank set, but a second parameter t ? wr-d permits earlier column operations to the opposite bank set. figure 44 shows how this is possible because there are two internal data buses s0 and s1. in this example, the four column read operations are made to the same bank bb, but they could use different banks as long as they all belonged to the bank set that was different from the bank set containing ba (for the column write operations). figure 43 write/read interaction ? no eraw feature figure 44 write/read interaction ? eraw feature t 0 t 1 t 2 t 3 cfm rq11..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn transaction a: wr a1 = {ba,ca1} a2 = {ba,ca2} transaction c: rd c1 = {bc,cc1} c2 = {bc,cc2} c2 rd t cwd q(c2) q(c1) t cac a1 wr d(a2) d(a1) t cycle c1 rd a2 wr t ? wr dq15..0 dqn15..0 t cc t wr-bub,xdrdram s[15:0] [15:0] t cc d(a1) d(a2) q(c1) q(c2) turnaround t 0 t 1 t 2 t 3 cfm rq11..0 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 cfmn transaction a: wr a1 = {ba,ca1} a2 = {ba,ca2} transaction b: rd b1 = {bb,cb1} b2 = {bb,cb2} b3 = {bb,cb3} c1 rd t cwd q(c1) q(b4) t cac a1 wr d(a2) d(a1) t cycle b4 rd a2 wr t ? wr-d dq15..0 dqn15..0 t cc s0[15:0] [15:0] t cc d(a1) d(a2) q(b4) q(c1) s1[15:0] [15:0] q(b1) q(b2) transaction c: rd c1 = {bc,cc1} b1 rd b3 rd b2 rd q(b2) q(b1) q(b3) q(b3) t wr-bub,xdrdram turnaround bb is in different bank set than ba bc is in same bank set as ba bank restrictions b4 = {bb,cb4}
preliminary data sheet e0643e30 (ver. 3.0) 55 edx5116abse figure 45 xdr dram block diagram with bank sets 1 1:2 demux reg 12 rq11..0 1:16 demux 16:1 mux 16/t cc bank 0 act . . . bank 0 1 act act row 1 1 pre pre pre row sense amp 0 . . . 1 1 r/w r/w col col col . . . . . . . . . bank array sense amp array ... dynamic width demux (wr) dq15..0 dqn15..0 16 16 16 16 16/t cc 16x16*2 6 16x16 16x16 16x16 16x16 3 3 3 6 12 (2 3 -2) bank (2 3 -2) sense amp 6 16x16*2 6 12 16x16*2 6 *2 12 16 d[15:0][15:0] s0[15:0][15:0] 16 16x16 16x16 16x16*2 6 q[15:0][15:0] dynamic width mux (rd) byte mask (wr) 12 6 ... ... 1 bank 0 . . . bank 1 1 act act row 1 1 pre pre row sense amp 1 1 1 r/w r/w col col .. . ... . .. bank array sense amp array 16x16*2 6 16x16 16x16 (2 3 -1) bank (2 3 -1) sense amp 6 16x16*2 6 12 16x16*2 6 *2 12 s1[15:0][15:0] 16x16*2 6 12 6 odd even act logic pre logic col logic decode decode decode ... ... ... ... ... ... wr even wr odd rd odd rd even ... ... ... ...
preliminary data sheet e0643e30 (ver. 3.0) 56 edx5116abse simultaneous activation when the xdr dram supports multiple bank sets as in figure 45, another feature may be supported, in addition to eraw. this feature is simultaneous activation, and the timing of several cases is shown in figure 46. the t rr parameter specifies the minimum spacing between packets with activation commands in xdr drams with a sin- gle bank set, or between packets to the same bank set in a xdr dram with multiple bank sets. the t rr-d parameter specifies the minimum spacing between packets with activation com- mands to different bank sets in a xdr dram with multiple bank sets. in figure 46, case 4 shows an example when both t rr and t rr- d must be at least 4*t cycle . in such a case, activation com- mands to different bank sets sati sfy the same constraint as acti- vation commands to the same bank set. in figure 46, case 2 shows an example when t rr must be at least 4*t cycle and t rr-d must be at least 2*t cycle . in such a case, an activation command to one bank set may be inserted between two activation commands to a different bank set. in figure 46, case 1 shows an example when t rr must be at least 4*t cycle and t rr-d must be at least 1*t cycle . as in the previous case, an activation command to one bank set may be inserted between two activation commands to a different bank set. in this case, the middle activation command will not be symmetrically placed relative to the two outer activation com- mands. in figure 46, case 0 shows an example when t rr must be at least 4*t cycle and t rr-d must be at least 0*t cycle . this means that two activation commands may be issued on the same cfm clock edge. this is only possible by using the delay mechanism in one of the two commands. see ?dynamic request scheduling? on page 20. in the example shown, the packet with the refa command is received one cycle before the command with the act command, and the refa com- mand includes a one cycle delay. both activation commands will be issued internally to different bank sets on the same cfm clock edge. figure 46 simultaneous activation ? t rr-d cases t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cycle dq15..0 dqn15..0 cfm cfmn rq11..0 t rr-d act refa act t rr-d case 4: t rr-d = 4*t cycle refa & act have same t rr t rr act refa act case 2: t rr-d = 2*t cycle refa fits between two act t rr-d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cycle dq15..0 dqn15..0 cfm cfmn rq11..0 case 1: t rr-d = 1*t cycle refa fits between two act t rr act refa act case 0: t rr-d = 0*t cycle refa simultaneous with act t rr-d t rr act refa act t rr-d (refa uses delay=1*t cycle ) set different from two act note - refa is directed to bank set different from two act note - refa is directed to bank set different from act at t 12 note - refa is directed to bank a a a a) edx5116abse does not support these cases. the minimum value of t rr-d is 4.
preliminary data sheet e0643e30 (ver. 3.0) 57 edx5116abse simultaneous precharge when the xdr dram supports multiple bank sets as in figure 45, another feature may be supported, in addition to eraw and simultaneous activation. this feature is simulta- neous precharge, and the timing of several cases is shown in figure 47. the t pp parameter specifies the minimum spacing between packets with precharge commands in xdr drams with a sin- gle bank set, or between packets to the same bank set in a xdr dram with multiple bank sets. the t pp-d parameter specifies the minimum spacing between packets with precharge com- mands to different bank sets in a xdr dram with multiple bank sets. in figure 46, case 4 shows an example when both t pp and t pp- d must be at least 4*t cycle . in such a case, precharge com- mands to different bank sets sati sfy the same constraint as pre- charge commands to the same bank set. in figure 46, case 2 shows an example when t pp must be at least 4*t cycle and t pp-d must be at least 2*t cycle . in such a case, a precharge command to one bank set may be inserted between two precharge commands to a different bank set. in figure 46, case 1 shows an example when t pp must be at least 4*t cycle and t pp-d must be at least 1*t cycle . as in the previous case, a precharge command to one bank set may be inserted between two precharge commands to a different bank set. in this case, the middle precharge command will not be symmetrically placed relative to the two outer precharge com- mands. in figure 46, case 0 shows an example when t pp must be at least 4*t cycle and t pp-d must be at least 0*t cycle . this means that two activation commands may be issued on the same cfm clock edge. this is possible by using the delay mechanism in one of the two commands. see ?dynamic request scheduling? on page 20. it is also possible by taking advantage of the fact that two independent precharge com- mands may be encoded within a single rowp packet. in the example shown, the rowp packet contains both a refa command and a pre command. both precharge commands will be issued internally to different bank sets on the same cfm clock edge. figure 47 simultaneous precharge ? t pp-d cases t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cycle dq15..0 dqn15..0 cfm cfmn rq11..0 t pp-d pre refp pre t pp-d case 4: t pp-d = 4*t cycle refp & pre have same t rr t pp pre refp pre case 2: t pp-d = 2*t cycle refp fits between two pre t pp-d t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 9 t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 8 t cycle dq15..0 dqn15..0 cfm cfmn rq11..0 case 1: t pp-d = 1*t cycle refp fits between two pre t pp pre pre case 0: t pp-d = 0*t cycle refp simultaneous with pre t pp-d t pp pre refp pre t pp-d set different from two pre note - refp is directed to bank set different from two pre note - refp is directed to bank set different from pre at t 12 note - refp is directed to bank refp a a) edx5116abse does not support case0. the minimum value of t pp-d is 1.
preliminary data sheet e0643e30 (ver. 3.0) 58 edx5116abse operating conditions electrical conditions table 12 summarizes all electric al conditions (temperature and voltage conditions) that may be applied to the memory compo- nent. the first section of parame ters is concerned with abso- lute voltages, storage, and ope rating temperatures, and the power supply, reference, and termination voltages. the second section of parameters determines the input voltage levels for the rsl rq signals. the high and low voltages must satisfy a symmetry parameter with respect to the v ref,rsl . the third section of parameters determines the input voltage levels for the rsl si (serial interface) signals. the high and low voltages must satisfy a symmetry parameter with respect to the v ref,rsl . the fourth section of parameters determines the input voltage levels for the cfm clock signals. the high and low voltages are specified by a common-mode value and a swing value. the fifth section of parameters determines the input voltage levels for the write data signals on the drsl dq pins. the high and low voltage are specified by a common-mode value and a swing value. table 12 electrical conditions symbol parameter minimum maximum unit v in,abs voltage applied to any pin (except vdd) with respect to gnd - 0.300 1.500 v v dd,abs voltage on vdd with respect to gnd - 0.500 2.300 v t store storage temperature - 50 100 c t j junction temperature under bi as during normal operation 0 100 c v dd supply voltage applied to vdd pins during normal operation 1.800 - 0.090 1.800 + 0.090 v v ref,rsl rsl - reference voltage applied to vref pin a v term,rsl - 0.450 - 0.025 v term,rsl - 0.450 + 0.025 v v term,drsl drsl - termination voltage applied to vterm pins 1.200 - 0.060 1.200 + 0.060 v v il,rq rsl rq inputs -low voltage v ref,rsl - 0.450 v ref,rsl - 0.150 v v ih,rq b rsl rq inputs -high voltage v ref,rsl + 0.150 v ref,rsl + 0.450 v r a,rq rsl rq inputs - data asymmetry: r a,rq = (v ih,rq -v ref,rsl )/(v ref,rsl -v il,rq ) 0.8 1.2 v v il,si rsl serial interface inputs -low voltage v ref,rsl - 0.450 v ref,rsl - 0.200 v v ih,si b rsl serial interface inputs -high voltage v ref,rsl + 0.200 v ref,rsl + 0.450 v r a,si rsl serial interface inputs - data asymmetry: r a,si = (v ih,si -v ref,rsl )/(v ref,rsl -v il,si ) 0.8 1.2 v v icm,cfm cfm/cfmn input - common mode: v icm,cfm = (v ih,cfm b +v il,cfm) /2 v term,drsl - 0.150 v term,drsl - 0.075 v v isw,cfm cfm/cfmn input - high-low swing: v isw,cfm = (v ih,cfm b - v il,cfm ) 0.150 0.300 v v icm,dq drsl dq inputs - common mode: v icm,dq = (v ih,dq b +v il,dq) /2 v term,drsl -0.150 v term,drsl -0.025 v v isw,dq drsl dq inputs - high-low swing: v isw,dq = (v ih,dq b - v il,dq ) 0.050 0.300 v a. v term,rsl is typically 1.200v0.060v. it c onnects to the rsl termination components, not to this dram component. b. v ih is typically equal to v term,rsl or v term,drsl (whichever is appropriate) unde r dc conditions in a system.
preliminary data sheet e0643e30 (ver. 3.0) 59 edx5116abse timing conditions table 13 summarizes all timing c onditions that may be applied to the memory component. the first section of parameters is concerned with parameters for the clock signals. the second section of parameters is conc erned with parameters for the request signals. the third secti on of parameters is concerned with parameters for the write data signals. the fourth section of parameters is concerned with parameters for the serial inter- face signals. the fifth secti on is concerned with all other parameters, including those for re fresh, calibration, power state transitions, and initialization. table 13 timing conditions symbol parameter and other conditions minimum maximum units figure(s) t cycle or t cyc,cfm cfm rsl clock - cycle time -4000 -3200 -2400 2.000 2.500 3.333 3.830 3.830 3.830 ns ns ns figure 48 t r,cfm , t f, cfm cfm/cfmn input - rise and fall time - use minimum for test. 0.080 0.200 t cycle figure 48 t h,cfm , t l,cfm cfm/cfmn input - high and low times 40% 60% t cycle figure 48 t r,rq , t f, rq rsl rq input - rise/fall times (20% - 80%) - use minimum for test. 0.080 0.260 t cycle figure 49 t s,rq , t h,rq rsl rq input to sample points @ 2.500 ns > t cycle 2.000 ns (set/hold) @ 3.333 ns > t cycle 2.500 ns @ 3.830 ns t cycle 3.333 ns 0.170 0.200 0.275 - - - ns ns ns figure 49 t ir,dq , t if,dq drsl dq input - rise/fall times (20% - 80%) - use minimum for test. 0.020 0.074 t cycle figure 50 t s,dq , t h,dq drsl dq input to sample points @ 2.500 ns > t cycle 2.000 ns (set/hold) @ 3.333 ns > t cycle 2.500 ns @ 3.830 ns t cycle 3.333 ns 0.052 0.065 0.080 - - - ns ns ns figure 50 t doff,dq drsl dq input delay offset (fixed) to sample points -0.080 +0.080 t cycle figure 50 t cyc,sck serial interface sck input - cycle time 20 - ns figure 52 t r,sck, t f,s ck serial interface sck input - rise and fall times - 5.0 ns figure 52 t h,sck , t l,sck serial interface sck input - high and low times 40% 60% t cyc,sck figure 52 t ir,si, t if,si serial interface cmd,rst,sdi input - rise and fall times - 5.0 ns figure 52 t s,si ,t h,si serial interface cmd,sdi input to sck clock edge - set/hold time 5 - ns figure 52 t dly,si-rq delay from last sck clock edge for register operation to first cfm edge with rq packet. also, delay from first cfm edge with rq packet to the first sck clock edge for register operation. 10 - t cyc,sck - t ref refresh interval. every row of every bank must be accessed at least once in this interval with a row-act, rowp-ref or rowp-refi command. - 16 ms figure 34 t refa-refa,avg average refresh command interval. rowp-refa or rowp-refi commands must be issued at this average rate. this depends upon t ref and the number of banks and rows: t refa-refa,avg = t ref /(n b *n r ) = t ref /(2 3 *2 12 ). t refa-refa,avg = 488 ns - n refa,burst refresh burst limit. the number of rowp-refa or rowp-refi commands which can be issued consecutively at the minimum command spacing. - 128 commands - t burst-refa refresh burst interval. the interval between a burst of n refa,burst,max rowp-refa or rowp-refi commands and the next rowp-refa or rowp-refi command. 40 - t cycle - t coreinit interval needed for core initialialization after power is applied. - 1.500 ms - t calc, t calz current calibration interval - 100 ms figure 35 t cmd-calc , t cmd-calz , delay between packet with any command w/ pre or refp command and calc/calz packet w/ any other command 4 16 - - t cycle figure 35 t calce , t calze delay between calc/calz packet and cale packet 12 - t cycle figure 35
preliminary data sheet e0643e30 (ver. 3.0) 60 edx5116abse operating characteristics electrical characteristics table 14 summarizes all electric al parameters (temperature, current, and voltage) that characterize this memory compo- nent. the only exception is the supply current values (i dd ) under different operating c onditions covered in the supply cur- rent profile section. the first section of parameters is concerned with the thermal characteristics of th e memory component. the second section of parameters is conc erned with the cur- rent needed by the rq pins and vref pin. the third section of parameters is concerned with the current needed by the dq pins and voltage levels produced by the dq pins when driving read data. this section is also concerned with the current needed by the vterm pin, and with the resistance levels produced for the internal termination compo- nents that attach to the dq pins. the fourth section of parameters determines the output volt- age levels and the current needed for the serial interface signals. t cale-cmd delay between cale packet and packet with any command 24 - t cycle figure 35 t cmd-pdn last command before pdn entry 16 - t cycle figure 36 t pdn-cfm rsl cfm/cfmn and vterm stable after pdn entry 16 - t cycle figure 36 t cfm-pdn rsl cfm/cfmn and vterm stable before pdn exit 16 - t cycle figure 36 t pdn-cmd first command after pdn exit (inc ludes lock time for cfm/cfmn) 4096 - t cycle figure 36 table 13 timing conditions (continued) symbol parameter and other conditions minimum maximum units figure(s) table 14 electrical characteristics symbol parameter minimum maximum units jc junction-to-case thermal resistance a - 0.5 c/watt i i,rsl rsl rq or serial inte rface input current @ (v in = v ih,rq,max ) -10 10 a i ref,rsl v ref,rsl current @ v ref,rsl,max flowing into vref pin -10 10 a v osw,dq drsl dq outputs - high-low swing: v osw,dq = (v ih,dq -v il,dqn ) or (v ih,dqn -v il,dq ) 0.200 0.400 v r term,dq drsl dq outputs - termination resistance 40.0 60.0 ? v ol,si rsl serial interface sdo output - low voltage 0.0 0.250 v v oh,si rsl serial interface sdo output - high voltage v term,rsl - 0.250 v term,rsl v a. the package is mounted on a thermal test board which is defined jedec standard jesd 51-9.
preliminary data sheet e0643e30 (ver. 3.0) 61 edx5116abse supply current profile in this section, table 15 summarizes the supply currents (i dd and i term,drsl ) that characterize this memory component. these parameters are shown un der different operating condi- tions. table 15 supply current profile symbol power state and steady state transaction rates maximum @t cycle = 2.000 ns @ x16/x8/x4 width maximum @t cycle = 2.500 ns @ x16/x8/x4 width maximum @t cycle = 3.333 ns @ x16/x8/x4 width units i dd,pdn device in pdn, self-refresh enabled. a tbd 25/25/25 tbd ma i dd,stby device in stby. this is for a device in stby with no packets on the channel a tbd 270/270/270 tbd ma i dd,row act command every t rr , pre command every t pp a tbd 600/600/600 tbd ma i dd,wr act command every t rr , pre command every t pp , wr command every t cc. a tbd 1200/1000/900 tbd ma i dd,rd act command every t rr , pre command every t pp , rd command every t cc a tbd 1300/1200/1100 tbd ma i term,drsl,wr wr command every t cc. b, c tbd 150/90/60 tbd ma i term,drsl,rd rd command every t cc. b tbd 290/150/90 tbd ma a. i dd current @ v dd,max flowing into vdd pins b. i term,drsl current @ v term,dq,max flowing into vterm pins c. mesurement condition: dq/dqn input swing level is 300mv.
preliminary data sheet e0643e30 (ver. 3.0) 62 edx5116abse timing characteristics table 16 summarizes all timing pa rameters that characterize this memory component. the only exceptions are the core timing parameters th at are speed-bin depe ndent. refer to the timing parameters section for more information. the first section of parameters pertains to the timing of the dq pins when driving read data. the second section of parameters is concerned with the tim- ing for the serial interface signals when driving register read data. the third section of parameters is concerned with the time intervals needed by the interf ace to transition between power states. timing parameters table 17 summarizes the timing parameters that characterize the core logic of this memory component. these timing parameters will vary as a func tion of the component?s speed bin. the four secti ons deal with the timing intervals between packets with, respectively, row-row commands, row-column commands, column-column commands, and column-row commands. table 16 timing characteristics symbol parameter and other conditions minimum maximum units figure(s) t q,dq drsl dq output delay (variation ac ross 16 q bits on each dq pin) from drive points - output delay @ 2.500 ns > t cycle 2.000 ns @ 3.333 ns > t cycle 2.500 ns @ 3.830 ns t cycle 3.333 ns -0.052 -0.065 -0.080 +0.052 +0.065 +0.080 ns ns ns figure 51 t qoff,dq drsl dq output delay offset (a fixed value for all 16 q bits on each dq pin) from drive points - output delay 0.000 +0.200 t cycle figure 51 t or,dq , t of,dq drsl dq output - rise and fall times (20%-80%). 0.020 0.040 t cycle figure 51 t q,si serial sck-to-sdo output delay @ c load,max = 15 pf 2 15 ns figure 53 t p, s i serial sdi-to-sdo propagation delay @ c load,max = 15 pf - 15 ns figure 53 t or,si , t of,si serial sdo output rise/fall (20%-80%) @ c load,max = 15 pf - 10 ns figure 53 t pdn-entry time for power state to change after pdn entry - 16 t cycle figure 36 t pdn-exit time for power state to change after pdn exit 0 - t cycle figure 36 table 17 timing parameters symbol parameter and other conditions min (a) min (b) min (c) units figure(s) t rc row-cycle time: interval between successive t rc rowa-act or rowp-refa or t rc-r, 2tcc = t rcd-r + t cc + t rdp + t rp a rowp-refi activate commands to the t rc-w, 2tcc, noeraw = t rcd-w + t cc + t wrp + t rp a same bank. t rc-w, 2tcc, eraw = t rcd-w + t cc + t wrp + t rp a 16 16 19 23 20 20 24 28 24 24 24 28 t cycle figure 4 - figure 7 t ras row-asserted time: interval between a rowa-act or rowp-refa or rowp-refi activate command and a rowp-pre or rowp-refp precharge command to the same bank. note that t ras,max is 64 us for all timing bins. 10 13 17 t cycle figure 4 - figure 7 t rp row-precharge time: interval between a rowp-pre or rowp-refp precharge command and a rowa-act or rowp-refa or rowp-refi activate command to the same bank. 6 7 7 t cycle figure 4 - figure 7 t pp precharge-to-precharge time: interval between successive rowp- t pp pre or rowp-refp precharge commands to different banks. t pp-d b 4 1 4 1 4 1 t cycle figure 4 - figure 7 t rr row-to-row time: interval between rowa-act or rowp- t rr refa or rowp-refi activate commands to different banks. t rr-d c 4 4 4 4 4 4 t cycle figure 4 - figure 7
preliminary data sheet e0643e30 (ver. 3.0) 63 edx5116abse t rcd-r row-to-column-read delay: interval between a rowa-act activate command and a col-rd read command to the same bank. 577t cycle figure 4 - figure 7 t rcd-w row-to-column-write delay: interval between a rowa-act activate command and a col- wr or col-wrm write co mmand to the same bank. 1 3 3 t cycle figure 4 - figure 7 t cac column access delay: interval from col-rd read command to q read data 6 7 7 t cycle figure 10 t cwd column write delay: interval from a col- wr or colm-wrm write command to d write data. 3 3 3 t cycle figure 9 t cc column-to-column time: interval between successive col-rd commands, or between succes- sive col-wr or colm-wrm commands. 2 2 2 t cycle figure 4 - figure 7 t rw-bub, xdrdram read-to-write bubble time: interval between the end of a q read data packet and the start of d write data packet (the end of a data packet is the time interval t cc after its start). 3 3 3 t cycle figure 13 t wr-bub, xdrdram write-to-read bubble time: interval between the end of a d writed data and the start of q read data packet (the end of a data packet is the time interval t cc after its start). 3 3 3 t cycle figure 13 t ? rw read-to-write time: interval between a col-rd read command and a col-wr or colm- wrm write command. d 8 9 9 t cycle figure 12 t ? wr write-to-read time: interval between a col-wr or t ? wr colm-wrm write command and a col-rd read command. t ? wr-d e 9 2 10 2 10 2 t cycle figure 12 t rdp read-to-precharge time: interval between a col-rd read command and a rowp-pre pre- charge command to the same bank. 3 4 4 t cycle figure 4 - figure 7 t wrp write-to-precharge time: interval between a col-wr or colm-wrm write command and a rowp-pre precharge command to the same bank. 10 12 12 t cycle figure 4 - figure 7 t dr write data-to-read time: interval between the start of d write data and a col-rd read com- mand to the same bank. 6 7 7 t cycle figure 12 t dp write data-to-precharge time: interval between d write data and rowp-pre precharge com- mand to the same bank. 7 9 9 t cycle figure 9 t lrrn-lrrn interval between rowp-lrrn command and a subsequent rowp-lrrn command. f 16 20 24 t cycle table 4 t refx-lrrn interval between rowp-refx command and a subsequent rowp-lrrn command. 16 20 24 t cycle table 4 t lrrn-refx interval between rowp-lrrn command and a subsequent rowp-refx command. 16 20 24 t cycle table 4 a. the t rc,min parameter is applicable to all transaction types (read, write, refresh, etc.). read and write transactions may have an additio nal limitation, depending upon how many column accesses (each requiring t cc ) are performed in each row access (t rc ). the table lists the special cases (t rc-r, 2tcc , t rc-w, 2tcc, noeraw , t rc-w, 2tcc, eraw ) in which two col- umn accesses are performed in each row access. note that t rc-w, 2tcc, eraw uses a relaxed value of t rcd-w that is equal to t rcd-r,min . all other parameters are minimum. b. t pp-d is the t pp parameter for precharges to different bank sets. see ?simultaneous precharge? on page 57. c. t rr-d is the t rr parameter for activates to di fferent bank sets. see ?simultaneous activation? on page 56. d. see ?propagation delay? on page 28. e. t ? wr-d is the t ? wr parameter for write-read accesses to different bank sets. see ?m ultiple bank sets and the eraw feature? on page 54. also, note that the value of t ? wr-d may not take on the values {3,5,7} within the range{t ? wr-d,min , ... t ? wr,min -1}. t ? wr-d may assume any value t ? wr,min . f. rowp-lrrn includes the commands {rowp-lrr0,rowp-lrr1,rowp-lrr2} rowp-refx includes the commands {rowp-refa,rowp-refi,rowp-refp} table 17 timing parameters (continued) symbol parameter and other conditions min (a) min (b) min (c) units figure(s)
preliminary data sheet e0643e30 (ver. 3.0) 64 edx5116abse receive/transmit timing clocking figure 48 shows a timing diagram for the cfm/cfmn clock pins of the memory component. this diagram represents a magnified view of these pins. this diagram shows only one clock cycle. cfm and cfmn are differential signals: one signal is the com- plement of the other. they are also high-true signals ? a low voltage represents a logical zero and a high voltage represents a logical one. there are two crossing points in each clock cycle. the primary crossing point incl udes the high-voltage-to-low- voltage transition of cfm (indicated with the arrowhead in the diagram). the secondary crossing point includes the low-volt- age-to-high-voltage transition of cfm. all timing events on the rsl signals are referenced to the first set of edges. timing events are measured to and from the crossing point of the cfm and cfmn signals. in the timing diagram, this is how the clock-cycle time (t cycle or t cyc,cfm ), clock-low time (t l,cfm ) and clock-high time (t h,cfm ) are measured. because timing intervals are measur ed in this fashion, it is nec- essary to constrain the slew rate of the signals. the rise (t r,cfm ) and fall time (t f,c fm ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v il,cfm + 0.2*(v ih,cfm -v il,cfm ) 80% = v il,cfm + 0.8*(v ih,cfm -v il,cfm ) figure 48 clocking waveforms cfm cfmn t cycle or t cyc,cfm t r,cfm 80% 20% v ih,cfm v il,cfm logic 0 logic 1 t l,cfm t h,cfm t f, c f m
preliminary data sheet e0643e30 (ver. 3.0) 65 edx5116abse rsl rq receive timing figure 49 shows a timing diagram for the rq11..0 request pins of the memory component. this diagram represents a magni- fied view of the pins and onl y a few clock cycles (cfm and cfmn are the clock signals). ti ming events are measured to and from the primary cfm/cfmn crossing point in which cfm makes its high-voltage-to-low-voltage transition. the rq11..0 signals are low-true: a high voltage represents a logical zero and a low voltage represents a logical one. timing events on the rq11..0 pins are measured to and from the point that the signal reaches the level of the reference voltage v ref,rsl . because timing intervals are measur ed in this fashion, it is nec- essary to constrain the slew rate of the signals. the rise (t r,rq ) and fall time (t f,rq ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v il,rq + 0.2*(v ih,rq -v il,rq ) 80% = v il,rq + 0.8*(v ih,rq -v il,rq ) there are two data receiving windows defined for each rq11..0 signal. the first of these (labeled ?0?) has a set time, t s,rq , and a hold time, t h,rq , measured around the primary cfm/cfmn crossing point. the second (labeled ?1?) has a set time (t s,rq ) and a hold time (t h,rq ) measured around a point 0.5*t cycle after the primary cfm/cfmn crossing point. figure 49 rsl rq receive waveforms t s,rq cfm cfmn rq0 t h,rq t cycle rq11 ... 80% 20% t r,rq v ih,rq v il,rq logic1 logic 0 v ref,rsl [1/2]?t cycle 0 1 t s,rq t h,rq t f, r q t s,rq t h,rq 80% 20% t r,rq v ih,rq v il,rq logic 1 logic 0 v ref,rsl [1/2]?t cycle 0 1 t s,rq t h,rq t f, r q
preliminary data sheet e0643e30 (ver. 3.0) 66 edx5116abse drsl dq receive timing figure 50 shows a timing diagram for receiving write data on the dq/dqn data pins of the memory component. this dia- gram represents a magnified view of the pins and shows only a few clock cycles are shown (cfm and cfmn are the clock sig- nals). timing events are meas ured to and from the primary cfm/cfmn crossing point in which cfm makes its high- voltage-to-low-voltage transition. the dq15..0/dqn15..0 signals are high-true: a low voltage represents a logical zero and a high voltage represents a logical one. they are also differen- tial ? timing events on the dq15..0/dqn15..0 pins are mea- sured to and from the point that each differential pair crosses. because timing intervals are measur ed in this fashion, it is nec- essary to constrain the slew rate of the signals. the rise time (t ir,dq ) and fall time (t if,dq ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v il,dq + 0.2*(v ih,dq -v il,dq ) 80% = v il,dq + 0.8*(v ih,dq -v il,dq ) there are 16 data receiving windows defined for each dq15..0/dqn15..0 pin pair. the receiving windows for a particular dqi/dqni pin pair is referenced to an offset parameter t doff,dqi (the index ?i? may take on the values {0, 1, ..15} and refers to each of the dq15..0/dqn15..0 pin pairs). the t doff,dqi parameter determines the time between the pri- mary cfm/cfmn crossing point and the offset point for the dqi/dqni pin pair. the 16 rece iving windows are placed at times t doff,dqi +(j/8)*t cycle (the index ?j? may take on the values {0,1, 2, ..15} and refers to each of the receiving win- dows for the dqi/dqni pin pair). the offset values t doff,dqi for each of the 16 dqi/dqni pin pairs can be different. however, each is constrained to lie inside the range {t doff,min , t doff,max }. furthermore, each offset value t doff,dqi is static and will not change during sys- tem operation. its value can be determined at initialization. the 16 receiving windows (j=0 ..15) for the first pair dq0/ dqn0 are labeled ?0? through ?15?. each window has a set time (t s,rq ) and a hold time (t h,rq ) measured around a point t doff,dq0 +(j/8)*t cycle after the primary cfm/cfmn crossing point. the 16 receiving windows (j=0..15) for the each of the other pairs dqi/dqni are also labele d ?0? through ?15?. each win- dow has a set time (t s,rq ) and a hold time (t h,rq ) measured around a point t doff,dqi +(j/8)*t cycle after the primary cfm/cfmn crossing point.
preliminary data sheet e0643e30 (ver. 3.0) 67 edx5116abse figure 50 drsl dq receive waveforms t s,dq cfm cfmn [(j)/8]?t cycle dq0 dqn0 t doff,dq0 1 2 0 5 6 3 4 j 14 15 t h,dq t cycle j = {0,1,2,3,4,5,6,7,8 ,9,10,11,12,13,14,15} dqi dqni t doff,dqi 1 2 0 5 6 3 4 j 14 15 1 2 0 5 6 3 4 j 14 15 t doff,min t doff,max ... ... ... ... ... ... ... ... v ih,dq v il,dq logic 0 logic 1 ... t s,dq [(j)/8]?t cycle t h,dq t s,dq [(j)/8]?t cycle t h,dq t if,dq t ir,dq t if,dq t ir,dq 80% 20% t if,dq t ir,dq v ih,dq v il,dq logic 0 logic 1 80% 20% v ih,dq v il,dq logic 0 logic 1 80% 20% i = {0,1,2,3,4,5,...15} ? dq15 dqn15 t doff,dq15
preliminary data sheet e0643e30 (ver. 3.0) 68 edx5116abse drsl dq transmit timing figure 51 shows a timing diagram for transmitting read data on the dq15..0/dqn15..0 data pins of the memory component. this diagram represents a magnified view of these pins and only a few clock cycles are shown (cfm and cfmn are the clock signals). timing events are measured to and from the pri- mary cfm/cfmn crossing poi nt in which cfm makes its high-voltage-to-low-voltage transition. the dq15..0/ dqn15..0 signals are high-true: a low voltage represents a log- ical zero and a high voltage represents a logical one. they are also differential ? timing ev ents on the dq15..0/dqn15..0 pins are measured to and from the point that each differential pair crosses. because timing intervals are measur ed in this fashion, it is nec- essary to constrain the slew rate of the signals. the rise (t or,dq ) and fall time (t of,dq ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v ol,dq + 0.2*(v oh,dq -v ol,dq ) 80% = v ol,dq + 0.8*(v oh,dq -v ol,dq ) there are 16 data transmit windows defined for each dq15..0/dqn15..0 pin pair. the transmitting windows for a particular dqi/dqni pin pair is referenced to an offset parameter t qoff,dqi (the index ?i? may take on the values {0, 1, ..15} and refers to each of the dq15..0/dqn15..0 pin pairs). the t qoff,dqi +t q,dq,max expression determines the time between the primary cfm/cfmn crossing point and the off- set point for the dqi/dqni pin pair. the offset values t qoff,dqi for each of the 16 dqi/dqni pin pairs can be different. however, each is constrained to lie inside the range {t qoff,min , t qoff,max }. furthermore, each offset value t qoff,dqi is static; its value will not change during system operation. its value can be determined at initialization time. the 16 transmit windows (j=0..15) for the first pair dq0/ dqn0 are labeled ?0? through ?15?. each window begins at the time (t qoff,dq0 +t q,dq,max +((j+0.5)/8)*t cycle ) and ends at the time (t qoff,dq0 +t q,dq,min +((j+1.5)/8)*t cycle ) measured after the primary cfm/cfmn crossing point. the 16 transmit windows (j=0 ..15) for the other pairs dqi/ dqni are also labeled ?0? through ?15?. each window begins at the time (t qoff,dqi +t q,dq,max +((j+0.5)/8)*t cycle ) and ends at the time (t qoff,dqi +t q,dq,min +((j+1.5)/8)*t cycle ) measured after the primary cfm/cfmn crossing point. note that when no read data is to be transmitted on the dq/ dqn pins (and no other compone nt is transmitting on the external dq/dqn wires), then the voltage level on the dq/ dqn pins will follow the voltage reference value vterm,drsl on the vterm pin. the logical value of each dq/dqn pin pair in this no-drive state will be ?1/1?; when read data is driven, each dq/dqn pin pair will have either the logical value of ?1/0? or ?0/1?.
preliminary data sheet e0643e30 (ver. 3.0) 69 edx5116abse figure 51 drsl dq transmit waveforms t q,dq,max cfm cfmn [(j+0.5)/8]?t cycle dq0 dqn0 t qoff,dq0 2 3 0 1 6 7 4 5 j 14 15 [(j-0.5)/8]?t cycle t q,dq,min t cycle j = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15} t q,dq,max [(j+0.5)/8]?t cycle dqi dqni t qoff,dqi 2 3 0 1 6 7 4 5 j 14 15 [(j-0.5)/8]?t cycle t q,dq,min t q,dq,max [(j+0.5)/8]?t cycle 2 3 0 1 6 7 4 5 j 14 15 [(j-0.5)/8]?t cycle t q,dq,min t qoff,min t qoff,max ... ... ... ... ... ... ... ... 80% 20% logic ?0? logic ?1? ... v oh,dq v ol,dq t of,dq t or,dq t of,dq t or,dq t of,dq t or,dq 80% 20% logic ?0? logic ?1? v oh,dq v ol,dq 80% 20% logic ?0? logic ?1? v oh,dq v ol,dq i = {0,1,2,3,4,5,...15} dq15 dqn15 t qoff,dq15
preliminary data sheet e0643e30 (ver. 3.0) 70 edx5116abse serial interface receive timing figure 52 shows a timing diagram for the serial interface pins of the memory component. this diagram represents a magni- fied view of the pins only a few clock cycles. the serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one. timing events are meas ured to and from the v ref,rsl level. because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. the rise time (t r,sck and t ir,si ) and fall time (t f,sck and t if,si ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v il,si + 0.2*(v ih,si -v il,si ) 50% = v il,si + 0.5*(v ih,si -v il,si ) 80% = v il,si + 0.8*(v ih,si -v il,si ) there is one receiving window defined for each serial interface signal (rst,cmd and sdi pins). this window has a set time (t s,rq ) and a hold time (t h,rq ) measured around the falling edge of the sck clock signal. figure 52 serial interface receive waveforms sck t cyc,sck 80% 20% t ir, si v ih,si v il,si logic 1 logic 0 v ref,rsl t s, si t h, si t if, si 80% 20% v ih,si v il,si logic 1 logic 0 v ref,rsl t l,sck t h,sck t f, s c k t r,sck rst cmd sdi
preliminary data sheet e0643e30 (ver. 3.0) 71 edx5116abse serial interface transmit timing figure 53 shows a timing diagram for the serial interface pins of the memory component. this diagram represents a magni- fied view of the pins and only a few clock cycles are shown. the serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one. timing events are meas ured to and from the v ref,rsl level. because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals. the rise time (t or,si ) and fall time (t of,si ) of the signals are measured from the 20% and 80% points of the full-swing levels. 20% = v ol,si + 0.2*(v oh,si -v ol,si ) 50% = v ol,si + 0.5*(v oh,si -v ol,si ) 80% = v ol,si + 0.8*(v oh,si -v ol,si ) there is one transmit window de fined for the serial interface data signal (sdo pins). this window has a maximum delay time (t q,si,max ) from the falling edge of the sck clock signal and a minimum delay time (t q,si,min ) from the next falling edge of the sck clock signal. when the memory component is not selected during a serial device read transaction, it w ill simply pass the information on the sdi input to the sdo output. this combinational propa- gation delay parameter is t p, s i . the t cyc,sck will need to be increased during a serial read transaction (relative to the t cyc,sck value for a serial write transaction) because of the accumulated propagation delay through all of the xdr dram devices on the serial interface. during initialization, when the serial identification is deter- mined, the sdi-to-sdo path is registered, so the t cyc,sck value can be set to the same va lue as for serial write transac- tions. see ?initialization? on page 46. figure 53 serial interface transmit waveforms sck t cyc,sck 80% 20% v ih,si v il,si logic 1 logic 0 v ref,rsl t l,sck t h,sck t f, s c k t r,sck 80% 20% t or,si v oh,si v ol,si logic 1 logic 0 v ref,rsl t q,si,max t q,si,min t of,si 80% 20% v ih,si v il,si logic 1 logic 0 v ref,rsl sdi t p, s i sdo combinational propagation from sdi to sdo when the device is not selected during a serial device read transaction.
preliminary data sheet e0643e30 (ver. 3.0) 72 edx5116abse package description package parasitic summary table 18 summarizes inductance, capacitance, and resistance values associated with each pin group for the memory compo- nent. most of the parameters have maximum values only, how- ever some have both maximum and minimum values. the first group of parameters are for the cfm/cfmn clock pair pins. they include inductance, capacitance, and resistance values. the second group of para meters are for the rq request pins. they include inductance, mutual inductance, capacitance, and resistance values. there are also limits on the spread in inductance and capacitance values allowed in any one memory component. the third group of pa rameters are specific to the dq data pins and include inductance, mutual inductance, capacitance, and resistance values. there are also limits on the spread in inductance and capaci tance values allowed in any one memory component.the fourth group of parameters are for the serial interface pins. they include inductance and capaci- tance values. table 18 package parasitic summary (package parasitic values are measured on randomly-sampled devices) symbol parameter and other co nditions minimum maximum units l vterm vterm pin - effective input inductance per four bits - 2.2 nh l i ,cfm cfm/cfmn pins - effe ctive input inductance b - 5.0 nh c i ,cfm cfm/cfmn pins - effect ive input capacitance b 1.8 2.4 pf r i ,cfm cfm/cfmn pins - effe ctive input resistance 4 18 ? l i ,rq rsl rq pins - effective input inductance b - 5.0 nh c i ,rq rsl rq pins - effective input capacitance b 1.8 2.4 pf r i ,rq rsl rq pins - effective input resistance 4 18 ? l 12,rq mutual inductance between adjacent rsl rq signals - 0.6 nh ? l i,rq difference in l i,rq between any rsl rq pins of a single device - 1.8 nh ? c i,rq difference in c i between cfm/cfmn average and rsl rq pins of single device -0.12 +0.12 pf z pkg,dq drsl dq pins - package differential impedance note - package trace length should be less than 10mm long. 70 130 ? c i ,dq drsl dq pins - effective input capacitance a - 1.8 pf ? c i,dq difference in c i between dqi and dqni of each drsl pair a - 0.06 pf r i ,dq drsl dq pins - effective input resistance 4 25 ? l i ,si serial interface effective input inductance b - 8.0 nh c i ,si serial interface effective input capacitance b (rst, sck, cmd) (sdi,sdo) 1.7 - 3.0 7.0 pf pf a. this is the effective die input capacitance, and does not include package capacitance. b. cfm/rq/si should include package capacitance / inductance, only dq does not include package capacitance. this value is a comb ination of the device io circuitry and pack- age capacitance & inductance.
preliminary data sheet e0643e30 (ver. 3.0) 73 edx5116abse figure 54 equivalent circuits for package parasitic gnd pin sck,cmd,rst pin pad l i,si c i,si gnd pin rq pin pad l i,rq r i,rq c i,rq rq pin l 12,rq rq pin l 12,rq cfm pin gnd pin gnd pin dq pin pad r i,dq c i,dq pad r i,dq c i,dq dqn pin z pkg,dq /2 z pkg,dq /2 pad r i,cfm c i,cfm pad r i,cfm c i,cfm cfmn pin sdi,sdo pin r term,dq r term,dq l i,cfm l i,cfm
preliminary data sheet e0643e30 (ver. 3.0) 74 edx5116abse package drawing 104-ball fbga ( bga) solder ball: lead free (sn-ag-cu) 15.18 0.1 0.2 sa 14.56 0.1 index mark 0.2 s b 0.10 s 0.10 s 0.40 0.05 s i ndex mark b 104- 0.50 0.05 0.12 msa b 1.27 12.7 2.0 12.0 0.8 a unit: mm eca-ts2-0147-01 1.05 0.1
preliminary data sheet e0643e30 (ver. 3.0) 75 edx5116abse package pin numbering figure 55 summarizes the device package?s pin assignments. figure 55 csp x16 package - pin numbering (top view) 1234567 p dq5 dq5n dq7n dq7 n gnd vdd vterm gnd m dq1 dq1n dq3n dq3 l gnd rq10 rq11 gnd k vdd rq8 rq9 vdd j vdd rq6 rq7 gnd h vref rq4 cfmn cfm g gnd rq2 rq5 gnd f vdd rq0 rq3 vdd e gnd rst rq1 gnd d sd0 cmd sck sdi c dq0 dq0n dq2n dq2 b gnd vdd vterm gnd a dq4 dq4n dq6n dq6 a8 not used when width is x1,x2,x4 not used when width is x1,x2,x4 not used when width is x1 not used when width is x1,x2,x4 not used when width is x1,x2 not used when width is x1,x2 not used when width is x1,x2,x4 lkjhgfedcba 1 dqn3 dqn9 vdd gnd vdd gnd vdd sdi dqn8 dqn2 2 dq3 dq9 vdd gnd dq8 dq2 3 dqn15 dqn5 vdd rq10 cfm rsrv rq4 rq0 dqn4 dqn14 4 dq15 dq5 gnd rq11 cfmn rsrv rq3 gnd dq4 dq14 5 vdd vdd vterm vdd vterm vdd vdd 6 gnd gnd gnd gnd gnd vdd vdd gnd gnd 7 8 9 10 11 gnd vterm gnd vdd gnd gnd vdd vterm gnd 12 vdd gnd gnd vdd gnd gnd vdd 13 dqn7 dqn13 vdd rq9 rq7 vref rq1 vdd dqn12 dqn6 14 dq7 dq13 cmd rq8 rq6 rq5 rq2 gnd dq12 dq6 15 dqn11 dqn1 sck rst dqn0 dqn10 16 dq11 dq1 gnd vdd vdd gnd vdd sdo dq0 dq10 a16
preliminary data sheet e0643e30 (ver. 3.0) 76 edx5116abse recommended soldering conditions please consult with our sales offices for soldering conditions of the edx5116abse. type of surface mount device edx5116abse: 104-ball fbga ( bga) < lead free (sn-ag-cu) >
preliminary data sheet e0643e30 (ver. 3.0) 77 edx5116abse notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
preliminary data sheet e0643e30 (ver. 3.0) 78 edx5116abse rambus and the rambus logo are trademarks or registered trademar ks of rambus inc. in the united states and other countries. rambus and other parties may also have trad emark rights in other terms used herein. bga is a registered trademark of tessera, inc. m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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